| 2015-04 | Logic soft error study with 800-MHz DDR3 SDRAMs in 3x nm using proton and neutron beams | 백상현 |
| 2008-03 | Low Power Configuration Strategy of TCAM Lookup | 백상현 |
| 2008-03 | Low power configuration strategy of TCAM lookup table | 백상현 |
| 2008-07 | Low Power Ternary Content-Addressable Memories (TCAM) Design Using Segmented Match-Line | 백상현 |
| 2008-07 | Low-Power Ternary Content-Addressable Memory Design Using a Segmented Match Line | 백상현 |
| 2013-04 | Memory Reliability Analysis for Multiple Block Effect of Soft Errors | 백상현 |
| 2010-04 | Minimizing Soft Errors in TCAM Devices: A Probabilistic Approach to Determining Scrubbing Intervals | 백상현 |
| 2011-10 | Mitigating the Effects of Large Multiple Cell Upsets (MCUs) in Memories | 백상현 |
| 2018-08 | Modeling and analysis of single-event transient sensitivity of a 65 nm clock tree | 백상현 |
| 2011-04 | Multiple cell upsets tolerant content-addressable memory | 백상현 |
| 2014-10 | Novel Error Detection Scheme With the Harmonious Use of Parity Codes, Well-Taps, and Interleaving Distance | 백상현 |
| 2009-08 | Null Detector Circuit Design Scheme for Detecting Defective AC-Coupled Capacitors in Differential Signaling | 백상현 |
| 2010-06 | Optimizing Scrubbing Sequences for Advanced Computer Memories | 백상현 |
| 2010-08 | Protection of Memories Suffering MCUs Through the Selection of the Optimal Interleaving Distance | 백상현 |
| 2022-08 | Quantification of Substrate Current Caused by an Individual Trap at Different Locations and Energies, Prevailing on Si/SiO2 Interface or Si Substrate of n-MOSFETs | 백상현 |
| 2017-05 | A Quatro-Based 65-nm Flip-Flop Circuit for Soft-Error Resilience | 백상현 |
| 2019-09 | Radiation Reliability Benefit of Area-Optimized Interleaved Flip-Flop Layout in 28 nm Technology | 백상현 |
| 2004-10 | Removing JTAG Bottleneck in System Interconnect Test | 백상현 |
| 2017-04 | Resource-Efficient SRAM-Based Ternary Content Addressable Memory | 백상현 |
| 2008-09 | Ring Oscillator를 이용한 신호의 동시 스위칭 밀도 분석 | 백상현 |
| 2009-09 | Selection of the optimal interleaving distance for memories suffering MCUs | 백상현 |
| 2018-05 | Signal characteristic and test exploitation for intermittent nanometer-scale cracks | 백상현 |
| 2014-11 | Single Event Resilient Dynamic Logic Designs | 백상현 |
| 2018-09 | A single event upset tolerant latch design | 백상현 |
| 2016-02 | Single-Event Transient Sensitivity Evaluation of Clock Networks at 28-nm CMOS Technology | 백상현 |
| 2012-11 | Soft error issues with scaling technologies | 백상현 |
| 2017-04 | Soft error study on DDR4 SDRAMs using a 480 MeV proton beam | 백상현 |
| 2013-11 | Soft error tolerant Content Addressable Memories (CAMs) using error detection codes and duplication | 백상현 |
| 2010-10 | SRAM cell reliability degradations due to cell crosstalk | 백상현 |
| 2009-08 | SRAM Interleaving Distance Selection With a Soft Error Failure Model | 백상현 |
