Efficient time multiplexed access mechanism for low power 3D-IC testing

Abstract

New technologies such as Big Data, AI and Internet-of-Things (IoT) are attracting attention. The interest and demand for semiconductor chips required for these technologies are also exploding. The market is demanding not only small but also high-performance semiconductor chips that provide various functions. In order to achieve small size as well as high performance, a method of increasing the degree of integration in a circuit using a microprocessor has been used. However, semiconductor microprocessing has reached its physical and cost limits. As a result, 3D-IC technology that stacks existing chips is emerging as an alternative to semiconductor microprocessing. 3D-ICs provide high capacity and performance, but their yield losses are high in the manufacturing process. The resulting yield test requires high power consumption, and the power consumption of the test is closely related to the test time. Since the test time in the semiconductor manufacturing process is directly related to the manufacturing cost, it is important to reduce the test time of the semiconductor chip. In this thesis, I present two methods for reducing the test cost of a 3D-IC. First, reconfigurable IEEE std. 1687 SIB structure eliminates unnecessary internal test circuitry from the test path while reducing test power consumption. Second, the temperature of the stacked die can be controlled by using TDM clock divider and clock controller. This method can prevent circuit damage by high temperature in testing and is also compatible with SIB structure. TDM clock divider and clock controller circuits are designed and simulated to verify the proposed method, which can reduce test power consumption and prevent damage to stacked die by heat.