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A Low-Power 10-bit Single-Slope ADC Using Power Gating and Multi-Clocks for CMOS Image Sensors

Title
A Low-Power 10-bit Single-Slope ADC Using Power Gating and Multi-Clocks for CMOS Image Sensors
Author
권오경
Keywords
single-slope ADC; CMOS image sensor; counter; comparator; shot noise
Issue Date
2016-10
Publisher
Institute of Electrical and Electronics Engineers
Citation
2016 International SoC Design Conference (ISOCC), Page. 262-263
Abstract
This paper proposes a low power 10-bit single-slope analog-to-digital converter (SS-ADC) for CMOS image sensors (CISs) with a column-parallel readout structure. The power consumption of the proposed SS-ADC is reduced by using a power gating scheme for the comparator and multi-clocks having different frequencies. The proposed SS-ADC was designed using a 0.13μm CIS process technology. The simulation results show that the power consumption of the proposed SS-ADC is 9.7 μW, which is 59.4 % less than that of the conventional SS-ADC.
URI
https://ieeexplore.ieee.org/document/7799775?arnumber=7799775&SID=EBSCO:edseeehttp://repository.hanyang.ac.kr/handle/20.500.11754/99137
ISBN
978-1-5090-3219-8
DOI
10.1109/ISOCC.2016.7799775
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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