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Time-Multiplexed 1687-Network for Test Cost Reduction

Title
Time-Multiplexed 1687-Network for Test Cost Reduction
Author
박성주
Keywords
Design-for-testability; IEEE std 1687; package-level test; scan test; time division multiplexing; wafer-level test
Issue Date
2018-08
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v. 37, No. 8, Page. 1681-1691
Abstract
The reconfigurable scan network standardized by IEEE std. 1687 offers flexibility in accessing the on-chip instruments, which significantly improves the test cost. In this paper, we present a novel time-multiplexed 1687-network architecture that significantly improves the absolute test application time of systems-on-chip at wafer-level as well as package-levels tests. This architecture leverages: 1) the ever increasing tester channel frequency; 2) the allowed test frequencies at the two test levels; and 3) the flexibility offered by the 1687-network. We also present a test-time calculation method for the proposed network architecture and use it in our experiments. Furthermore, we study the effects of the number of time slots on different parameters.
URI
https://ieeexplore.ieee.org/abstract/document/8081843http://repository.hanyang.ac.kr/handle/20.500.11754/81313
ISSN
0278-0070
DOI
10.1109/TCAD.2017.2766146
Appears in Collections:
COLLEGE OF COMPUTING[E] > COMPUTER SCIENCE(소프트웨어학부) > Articles
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