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dc.contributor.author권오경-
dc.date.accessioned2018-11-15T06:52:45Z-
dc.date.available2018-11-15T06:52:45Z-
dc.date.issued2016-09-
dc.identifier.citationIEEE TRANSACTIONS ON ELECTRON DEVICES, v. 63, NO. 9, Page. 3599-3604en_US
dc.identifier.issn0018-9383-
dc.identifier.issn1557-9646-
dc.identifier.urihttps://ieeexplore.ieee.org/document/7515162-
dc.identifier.urihttp://repository.hanyang.ac.kr/handle/20.500.11754/80446-
dc.description.abstractThis paper presents an area-efficient and low-power 12-b successive approximation register/single-slope analog-to-digital converter (SAR/SS ADC) for CMOS image sensor (CIS) applications. The number of unit capacitors of the proposed SAR/SS ADC is reduced to 1/64th of that of a conventional 12-b SAR ADC using only a 6-b capacitor digital-to-analog converter (DAC) and the power consumption is reduced by sharing analog circuits between the SAR ADC and the SS ADC. In addition, the proposed ADC properly operates without using any calibration method as it is designed to be robust to inaccuracies in analog circuits by connecting the ramp signal to the bottom plate of the unit capacitor in the capacitor DAC. A 1936 x 840 pixel 60 frames/s CIS with the proposed SAR/SS ADCs was fabricated using a 90-nm CMOS process, and each readout channel with the proposed SAR/SS ADC occupies an area of 2.24 mu m x 998 mu m and consumes a power of 30 mu W. The measurement results show that the SAR/SS ADC has a differential nonlinearity of -0.45/+0.84 LSB and an integral nonlinearity of -1.5/+0.74 LSB. In addition, the developed CIS has a temporal noise of 2.7 LSBrms and a column fixed pattern noise of 0.07 LSB.en_US
dc.description.sponsorshipThis work was supported by the Industrial and Educational Cooperative Research and Development Program through SK Hynix Semiconductor Inc., and through Hanyang University. The review of this paper was arranged by Editor A. Bermak.en_US
dc.language.isoenen_US
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCen_US
dc.subjectCMOS image sensor (CIS)en_US
dc.subjectcolumn-parallel readouten_US
dc.subjecthybrid analog-to-digital converter (ADC)en_US
dc.subjectsingle-slope (SS) ADCen_US
dc.subjectsuccessive approximation ADCen_US
dc.titleAn Area-Efficient and Low-Power 12-b SAR/Single-Slope ADC Without Calibration Method for CMOS Image Sensorsen_US
dc.typeArticleen_US
dc.relation.no9-
dc.relation.volume63-
dc.identifier.doi10.1109/TED.2016.2587721-
dc.relation.page3599-3604-
dc.relation.journalIEEE TRANSACTIONS ON ELECTRON DEVICES-
dc.contributor.googleauthorKim, Min-Kyu-
dc.contributor.googleauthorHong, Seong-Kwan-
dc.contributor.googleauthorKwon, Oh-Kyong-
dc.relation.code2016003031-
dc.sector.campusS-
dc.sector.daehakCOLLEGE OF ENGINEERING[S]-
dc.sector.departmentDEPARTMENT OF ELECTRONIC ENGINEERING-
dc.identifier.pidokwon-
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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