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An Area-Efficient and Low-Power 12-b SAR/Single-Slope ADC Without Calibration Method for CMOS Image Sensors

Title
An Area-Efficient and Low-Power 12-b SAR/Single-Slope ADC Without Calibration Method for CMOS Image Sensors
Author
권오경
Keywords
CMOS image sensor (CIS); column-parallel readout; hybrid analog-to-digital converter (ADC); single-slope (SS) ADC; successive approximation ADC
Issue Date
2016-09
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation
IEEE TRANSACTIONS ON ELECTRON DEVICES, v. 63, NO. 9, Page. 3599-3604
Abstract
This paper presents an area-efficient and low-power 12-b successive approximation register/single-slope analog-to-digital converter (SAR/SS ADC) for CMOS image sensor (CIS) applications. The number of unit capacitors of the proposed SAR/SS ADC is reduced to 1/64th of that of a conventional 12-b SAR ADC using only a 6-b capacitor digital-to-analog converter (DAC) and the power consumption is reduced by sharing analog circuits between the SAR ADC and the SS ADC. In addition, the proposed ADC properly operates without using any calibration method as it is designed to be robust to inaccuracies in analog circuits by connecting the ramp signal to the bottom plate of the unit capacitor in the capacitor DAC. A 1936 x 840 pixel 60 frames/s CIS with the proposed SAR/SS ADCs was fabricated using a 90-nm CMOS process, and each readout channel with the proposed SAR/SS ADC occupies an area of 2.24 mu m x 998 mu m and consumes a power of 30 mu W. The measurement results show that the SAR/SS ADC has a differential nonlinearity of -0.45/+0.84 LSB and an integral nonlinearity of -1.5/+0.74 LSB. In addition, the developed CIS has a temporal noise of 2.7 LSBrms and a column fixed pattern noise of 0.07 LSB.
URI
https://ieeexplore.ieee.org/document/7515162http://repository.hanyang.ac.kr/handle/20.500.11754/80446
ISSN
0018-9383; 1557-9646
DOI
10.1109/TED.2016.2587721
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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