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Drop-shock reliability improvement of embedded chip resistor packages through via structure modification

Title
Drop-shock reliability improvement of embedded chip resistor packages through via structure modification
Author
김영호
Keywords
Embedded passive device; Embedded chip resistor substrate; Drop-shock reliability; PCB via structure; Cu interconnection with chip
Issue Date
2016-08
Publisher
PERGAMON-ELSEVIER SCIENCE LTD
Citation
MICROELECTRONICS RELIABILITY, v. 63, Page. 194-200
Abstract
We investigated the drop-shock reliability of embedded chip resistor package substrates and the effect of via structure on fractures after reflow and isothermal aging. The drop reliability of an embedded chip resistor package was evaluated under the JESD22-B111 condition. Chip resistors were embedded in Printed Circuit Board (PCB) and electrically interconnected through laser drilling and Cu plating with chip resistors. In order to improve drop reliability, via structures were modified and the Modified via structure was realized by altering the laser beam distribution to transfer the fracture locus (or site) from brittle intermetallic interfaces to ductile metal interfaces such as Cu, Ni, and Ag in a chip resistor. The modified Cu via interconnection structure was extremely effective in lowering the crack propagation rate and decreasing the stress concentration factor, since this structure hindered fractures from propagating to the brittle interface between intermetallic layers during drop shock tests. (C) 2016 Elsevier Ltd. All rights reserved.
URI
https://www.sciencedirect.com/science/article/pii/S0026271416301007?via%3Dihubhttp://repository.hanyang.ac.kr/handle/20.500.11754/76404
ISSN
0026-2714
DOI
10.1016/j.microrel.2016.05.003
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > MATERIALS SCIENCE AND ENGINEERING(신소재공학부) > Articles
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