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Clock- and Data-Recovery Circuit With Independently Controlled Eye-Tracking Loop for High-Speed Graphic DRAMs

Title
Clock- and Data-Recovery Circuit With Independently Controlled Eye-Tracking Loop for High-Speed Graphic DRAMs
Author
권오경
Keywords
Bang-bang phase detector (PD); clock and data recovery (CDR); complementary metal-oxide-semiconductor (CMOS); dynamic random access memory (DRAM); eye tracking; jitter tolerance
Issue Date
2011-07
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA
Citation
IEEE Transactions on Circuits and Systems II: Express Briefs IEEE Trans. Circuits Syst. II Circuits and Systems II: Express Briefs, IEEE Transactions on. 58(7):422-426 Jul, 2011
Abstract
An independently controlled eye-tracking clock- and data-recovery (CDR) circuit that achieves enhanced high-frequency jitter tolerance is presented in this brief. In the proposed CDR, a data-tracking loop compensates interchannel timing skews and rejects low-frequency jitter of the data, and an eye-tracking loop tracks asymmetric jitter distribution and high-frequency jitter of the data to enhance high-frequency jitter tolerance. This can be achieved by independently controlling two loops in the digital domain. The CDR is implemented using an 0.18-mu m CMOS process, and a bit error rate of less than 10(-12) was achieved for a data rate up to 5.8 Gb/s using a 2(31) - 1 pseudorandom binary-sequence input.
URI
https://ieeexplore.ieee.org/document/5940211/http://repository.hanyang.ac.kr/handle/20.500.11754/72923
ISSN
1558-3791; 1549-7747
DOI
10.1109/TCSII.2011.2158254
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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