41 0

Reduce Cell to Cell Charge Interference by Virtual Ground Inclusion in 3-Dimensional Vertical Gate NAND Flash Memory

Title
Reduce Cell to Cell Charge Interference by Virtual Ground Inclusion in 3-Dimensional Vertical Gate NAND Flash Memory
Author
이승백
Keywords
BICS; VG NAND; MONOS; Charge Interference; Virtual Ground
Issue Date
2011-06
Publisher
American Scientific Publishers
Citation
JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, JUL 2011, 11(7), p5865-p5869, 5p.
Abstract
In this work, we propose a structural modification to the 3-dimensional vertical gate NAND flash memory that will reduce the charge interference caused by stored charge on the opposite facing cell. In the barrier oxide structure (BOS), an oxide layer was inserted into the center of the body to physically block the conduction electrons moving to and from the channel regions influenced by the charge stored on either of the Oxide-Nitride-Oxide (ONO) trap layers. In the virtual ground structure (VGS), a highly p-type doped poly silicon layer was inserted to act as a virtual ground to reduce the electric-field changes caused by the stored change on the ONO trap layers. We investigated the I-V characteristics of the different structures using 3-D TOAD simulation tool, depending on the body type (crystalline or poly silicon) at double programming and single programming. We confirmed that the charge interference problem was reduced significantly by the BOS and VGS modifications in the crystalline silicon and high quality poly silicon body structures.
URI
http://www.ingentaconnect.com/content/asp/jnn/2011/00000011/00000007/art00047#http://repository.hanyang.ac.kr/handle/20.500.11754/72865
ISSN
1533-4880
DOI
10.1166/jnn.2011.4469
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
Files in This Item:
There are no files associated with this item.
Export
RIS (EndNote)
XLS (Excel)
XML


qrcode

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

BROWSE