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dc.contributor.author김태환-
dc.date.accessioned2018-07-25T00:14:44Z-
dc.date.available2018-07-25T00:14:44Z-
dc.date.issued2011-02-
dc.identifier.citationJOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY,권: 11 호: 2 페이지: 1337-1341en_US
dc.identifier.issn1533-4880-
dc.identifier.urihttp://www.ingentaconnect.com/content/asp/jnn/2011/00000011/00000002/art00066;jsessionid=36wj0d6mpm405.x-ic-live-01-
dc.identifier.urihttp://repository.hanyang.ac.kr/handle/20.500.11754/72772-
dc.description.abstractNanoscale two-bit/cell NAND silicon-oxide-nitride-oxide-silicon flash memory devices based on a separated double-gate (SDG) saddle structure with a recess channel region had two different doping regions in silicon-fin channel to operate two-bit per cell. A simulation results showed that the short channel effect, the cross-talk problem between cells, and the increase in threshold voltage distribution were minimized, resulting in the enhancement of the scaling-down characteristics and the program/erase speed.en_US
dc.language.isoenen_US
dc.publisherAMER SCIENTIFIC PUBLISHERS, 25650 NORTH LEWIS WAY, STEVENSON RANCH, CA 91381-1439 USAen_US
dc.subjectNAND Flash Memoryen_US
dc.subjectSaddleen_US
dc.subjectDouble-Gateen_US
dc.subjectSONOSen_US
dc.subjectTwo-Bit/Cellen_US
dc.subjectNVMen_US
dc.titleNanoscale Two-Bit/Cell NAND Silicon-Oxide-Nitride-Oxide-Silicon Devices with a Separated Double-Gate Saddle-Type Structureen_US
dc.typeArticleen_US
dc.relation.no2-
dc.relation.volume11-
dc.identifier.doi10.1166/jnn.2011.3373-
dc.relation.page1337-1341-
dc.relation.journalJOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY-
dc.contributor.googleauthorPark, Sang Su-
dc.contributor.googleauthorYou, Joo Hyung-
dc.contributor.googleauthorKwack, Kae Dal-
dc.contributor.googleauthorKim, Tae Whan-
dc.relation.code2011214452-
dc.sector.campusS-
dc.sector.daehakCOLLEGE OF ENGINEERING[S]-
dc.sector.departmentDEPARTMENT OF ELECTRONIC ENGINEERING-
dc.identifier.pidtwk-
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COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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