A capacitorless low-dropout regulator with enhanced slew rate and 4.5-μA quiescent current

Title
A capacitorless low-dropout regulator with enhanced slew rate and 4.5-μA quiescent current
Author
노정진
Keywords
Voltage regulator; Low-dropout regulator; High slew rate; LOW-QUIESCENT CURRENT; LDO REGULATOR; CMOS; TECHNOLOGY
Issue Date
2017-01
Publisher
SPRINGER
Citation
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, v. 90, No. 1, Page. 227-235
Abstract
In this paper, an output-capacitorless, low-dropout (LDO) voltage regulator with excellent load regulation and fast recovery time was designed using two amplifiers, which provided high gain, high bandwidth (HBW), and high slew rate (HSR). In addition, a one-shot current boosting (OSCB) circuit was added for current control to charge and discharge the parasitic capacitance at the power transistor gate during the load-current transition to improve the response time. The experimental results show that the proposed LDO regulator consumes a quiescent current of only 4.5 μA and can deliver a maximum load current of 200 mA, while regulating the output voltage at 1\,V with a 1.2 V power supply. We experimentally verified that for a current transition from 0.1 to 200 mA, the undershoot and overshoot voltages were 260 and 190\,mV, with recovery times of only 0.8 and 0.85 μs, respectively.
URI
https://link.springer.com/article/10.1007/s10470-016-0869-zhttp://repository.hanyang.ac.kr/handle/20.500.11754/71643
ISSN
0925-1030; 1573-1979
DOI
10.1007/s10470-016-0869-z
Appears in Collections:
COLLEGE OF ENGINEERING SCIENCES[E](공학대학) > ELECTRICAL ENGINEERING(전자공학부) > Articles
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