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Yield Prediction for Integrated Circuits Manufacturing Through Hierarchical Bayesian Modeling of Spatial Defects

Title
Yield Prediction for Integrated Circuits Manufacturing Through Hierarchical Bayesian Modeling of Spatial Defects
Author
배석주
Keywords
Semiconductor device modeling; Integrated circuit modeling; Yield estimation; Bayesian methods; Data models; Integrated circuit manufacture
Issue Date
2011-12
Publisher
IEEE INSTITUTE OF ELECTRICAL AND ELECTRONICS
Citation
IEEE transactions on reliability, 2011, 60(4), P.729-741
Abstract
Accurate yield prediction to evaluate productivity, and to estimate production costs, is a critical issue in the highly competitive semiconductor industry. We propose yield models based on hierarchical Bayesian modeling of clustered spatial defects produced in integrated circuits (IC) manufacturing. We use spatial locations of the IC chips on the wafers as covariates, and develop four models based on Poisson regression, negative binomial (NB) regression, zero-inflated Poisson (ZIP) regression, and zero-inflated negative binomial (ZINB) regression. Along with the hierarchical Bayesian approaches, spatial variations of defects within one wafer as well as among different wafers are effectively incorporated in the yield models. Wafermap data obtained from an industrial collaborator are used to illustrate the proposed models. The results indicate that the Poisson regression model consistently underestimates the true yield because of extraneous Poisson variation caused by defect clustering. On the contrary, NB regression, ZIP regression, and ZINB regression models provide more reliable yield estimation and prediction in real applications.
URI
https://ieeexplore.ieee.org/abstract/document/5957294/http://repository.hanyang.ac.kr/handle/20.500.11754/70560
ISSN
0018-9529
DOI
10.1109/TR.2011.2161698
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > INDUSTRIAL ENGINEERING(산업공학과) > Articles
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