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Low-Power 10-Gb/s Transmitter for High-Speed Graphic DRAMs Using 0.18-mu m CMOS Technology

Title
Low-Power 10-Gb/s Transmitter for High-Speed Graphic DRAMs Using 0.18-mu m CMOS Technology
Author
권오경
Keywords
Multiplexing; Transmitters; Random access memory; Bandwidth; Logic gates; CMOS integrated circuits
Issue Date
2011-12
Publisher
Institute of Electrical and Electronics Engineers
Citation
IEEE Transactions on Circuits and Systems II-Express Briefs, 2011, 58(12), P.921~925
Abstract
This brief presents a 10-Gb/s transmitter using a low-power one-stage 8:1 multiplexer. In the proposed transmitter, a differential current-steering output driver with a multiphase multiplexer architecture is used to alleviate speed limitations of the DRAM process. The current-steering output driver reduces the required output swing and increases the bandwidth of the multiplexer. The proposed multiplexer accomplishes not only high-speed operation but also low power dissipation by using a pseudo-nMOS configuration with one-stacked switches and reducing the short-circuit current of the gate driver in the multiplexer. The prototype of the transmitter using a 0.18-µm CMOS technology achieves the power efficiency of 5.69 mW/Gb/s at the data rate of 10 Gb/s.
URI
https://ieeexplore.ieee.org/abstract/document/6092473/http://repository.hanyang.ac.kr/handle/20.500.11754/70556
ISSN
1057-7130
DOI
10.1109/TCSII.2011.2172716
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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