3차원 집적을 위한 수소 이온 주입 기반 웨이퍼 본딩 및 분석

Abstract

Ion-cut base Si wafer cleavage technology is able to process the 3D integration circuit by stacking thin Si on a fabricated device wafer, which lead to a reduction in the parasitic capacitance and leakage current. Semiconductor has been developed to improve the performance with scaling down. But the scaling down technology has approached the physical limit. So most of the researchers have suggested the 3D stacking integration scheme as Through Silicon Via (TSV) and Monolithic 3D (M3D) which will result the high density and higher performance of the devices. Especially M3D integration receives more attention than TSV structure due to smaller via size (~um), which meant to be able to extract the low power consumption as low as we can reduce via size. But we have to consider the thermal budget during the stacking of the top device process, because the M3D structure was proceeding with being fabricated device in bottom wafer. The hydrogen H layer is implanted in Si substrate using appropriate power and dose. The implant power, dose and bonding strength affected the diverse mechanism of channel transfer such as channel depth and surface energy. So we demonstrated the low temperature impact with ion implant dose(from 2E16 ions/cm2 to 2E17 ions/cm2) and diverse of deposition oxide(Dry, HDP, TEOS), which had to proceed the low annealing process ranges of 400 to 500℃. The hydrogen implantation has tendency the formed deeper H+ layer according to increasing dose leading compressive stress, which was analyzed by SIMS, TEM and wafer curvature. The effect of different deposition technique on the bonding strength was analyzed by ‘Razor’ blade test. That mechanism decided the channel which was supposed to be transferred. As a result, we used optimized condition for channel transferring on fabricated device with height of 3.5um. After channel transfer, we reduced the roughness in order to extract the improved electric performance with CMP process for 500sec, which obtained thin layer from 300nm to 70nm on device bottom wafer. Finally we demonstrate the M3D platform process through implant, bonding and CMP process with low temperature annealing.