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Modified wirte-and-verify scheme for improving the endurance of multi-level cell phase-change memory using Ge-doped SbTe

Title
Modified wirte-and-verify scheme for improving the endurance of multi-level cell phase-change memory using Ge-doped SbTe
Author
정두석
Keywords
Modified WAV scheme; Endurance improvement; Phase-change memory
Issue Date
2012-10
Publisher
Elsevier
Citation
Solid-State Electronics, 2012, 76, 67p ~ 70p
Abstract
In this study, a modified write-and-verify (WAV) scheme is proposed for improving the programming/erasing (P/E) endurance of multi-level cell (MLC) phase-change memory (PCM) using Ge-doped SbTe (GeST). A dual reference data read method is developed to detect the level margin decay during P/E cycling, and a trigger condition is designed to trigger self-repair for the degraded cells before any P/E error for the modified WAV scheme. Experimental results suggest that the modified WAV scheme effectively extends the P/E endurance of PCM using GeST during 4-level P/E by at least 10 times. The modified WAV scheme is expected to improve the endurance of MLC–PCM of system applications.
URI
https://www.sciencedirect.com/science/article/pii/S0038110112002110http://hdl.handle.net/20.500.11754/67219
ISSN
0038-1101
DOI
10.1016/j.sse.2012.06.003
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > MATERIALS SCIENCE AND ENGINEERING(신소재공학부) > Articles
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