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Reduced Distribution of Threshold Voltage Shift in Double Layer NiSi2 Nanocrystals for Nano-Floating Gate Memory Applications

Title
Reduced Distribution of Threshold Voltage Shift in Double Layer NiSi2 Nanocrystals for Nano-Floating Gate Memory Applications
Author
이승백
Keywords
DOUBLE LAYER; NANO FLOATING GATE MEMORY; NANOCRYSTALS; NISI2
Issue Date
2011-12
Publisher
American Scientific Publishers
Citation
Journal of Nanoscience and Nanotechnology, 2011, 11(12), P.10553~10559
Abstract
We report on the fabrication and capacitance-voltage characteristics of double layer nickel-silicide nanocrystals with Si3N4 interlayer tunnel barrier for nano-floating gate memory applications. Compared with devices using SiO2 interlayer, the use of Si3N4 interlayer separation reduced the average size (4 nm) and distribution (+/- 2.5 nm) of NiSi2 nanocrystal (NC) charge traps by more than 50% and giving a two fold increase in NC density to 2.3 x 10(12) cm(-2). The increased density and reduced NC size distribution resulted in a significantly decrease in the distribution of the device C-V characteristics. For each program voltage, the distribution of the shift in the threshold voltage was reduced by more than 50% on average to less than 0.7 V demonstrating possible multi-level-cell operation.
URI
http://www.ingentaconnect.com/content/asp/jnn/2011/00000011/00000012/art00048http://hdl.handle.net/20.500.11754/66813
ISSN
1533-4880
DOI
10.1166/jnn.2011.4009
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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