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Zero bit error rate ID generation circuit using via formation probability in 0.18 mu m CMOS process

Title
Zero bit error rate ID generation circuit using via formation probability in 0.18 mu m CMOS process
Author
최병덕
Issue Date
2014-06
Publisher
INST ENGINEERING TECHNOLOGY-IET, MICHAEL FARADAY HOUSE SIX HILLS WAY STEVENAGE, HERTFORD SG1 2AY, ENGLAND
Citation
ELECTRONICS LETTERS,50(12),p.876-877
Abstract
An integrated circuit for a physical unclonable function (PUF) to generate an identifier for each device is proposed based on the via formation probability. The via hole size is determined to be smaller than that specified by the design rule which guarantees successful via formation. As a result, a via is formed with a certain probability. A proper via hole size and a post-processing method are found to obtain very high randomness in the bit sequences, and it is confirmed that the bit error rate is zero through repeated measurements over one year under the supply voltage variations with noises and in a wide range of temperature. This time invariance of bits can be attributed to the fact that the via formation does not change over time, once they are formed.
URI
http://ieeexplore.ieee.org/document/6836726/http://hdl.handle.net/20.500.11754/56292
ISSN
0013-5194; 1350-911X
DOI
10.1049/el.2013.3474
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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