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dc.contributor.author유창식-
dc.date.accessioned2018-04-02T02:14:56Z-
dc.date.available2018-04-02T02:14:56Z-
dc.date.issued2014-06-
dc.identifier.citationIEICE ELECTRONICS EXPRESS, 11(11), 20140351pen_US
dc.identifier.issn1349-2543-
dc.identifier.urihttp://www.jstage.jst.go.jp/article/elex/11/11/11_11.20140351/_article/-char/en-
dc.identifier.urihttp://hdl.handle.net/20.500.11754/54731-
dc.description.abstractA clock and data recovery (CDR) circuit for 1.5-5.0 Gb/s wireline transceiver is described. A phase locked loop (PLL) with dual phase frequency detector (PFD) and charge pump (CP) pairs performs the seamless phase rotation for the CDR circuit to track the phase and frequency difference. The CDR circuit implemented in a 65 nm CMOS process consumes 22.8 mW from a 1.2 V supply at 5.0 Gb/s. For 25 MHz jitter frequency, the CDR circuit can tolerate up to 0.21 unit-interval (UI) jitter with bit error rate (BER) smaller than 10(-12).en_US
dc.description.sponsorshipThis work is sponsored by IT R&D program MKE/KEIT (No. 10035202, Large Scale hyper-MLC SSD Technology Development) and the National Research Foundation of Korea (NRF) grant funded by the Korea Government (MSIP) (No. 2013R1A2A2A01004958). The CAD tools were provided by IC Design Education Center (IDEC), KAIST, Korea.en_US
dc.language.isoenen_US
dc.publisherIEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, KIKAI-SHINKO-KAIKAN BLDG, 3-5-8, SHIBA-KOEN, MINATO-KU, TOKYO, 105-0011, JAPANen_US
dc.subjectclock and data recovery (CDR)en_US
dc.subjectwireline transceiveren_US
dc.subjectphase locked loop (PLL)en_US
dc.subjectphase rotationen_US
dc.subjectCMOSen_US
dc.titleA 1.5-5.0 Gb/s clock and data recovery circuit with dual-PFD phase-rotating phase locked loopen_US
dc.title.alternatives clock and data recovery circuit with dual-PFD phase-rotating phase locked loopen_US
dc.typeArticleen_US
dc.relation.no11-
dc.relation.volume11-
dc.identifier.doi10.1587/elex.11.20140351-
dc.relation.page0-0-
dc.relation.journalIEICE ELECTRONICS EXPRESS-
dc.contributor.googleauthorChoi, Dong-Ho-
dc.contributor.googleauthorYoo, Chang-sik-
dc.relation.code2014030895-
dc.sector.campusS-
dc.sector.daehakCOLLEGE OF ENGINEERING[S]-
dc.sector.departmentDEPARTMENT OF ELECTRONIC ENGINEERING-
dc.identifier.pidcsyoo-
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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