A 1.5-5.0 Gb/s clock and data recovery circuit with dual-PFD phase-rotating phase locked loop

Title
A 1.5-5.0 Gb/s clock and data recovery circuit with dual-PFD phase-rotating phase locked loop
Other Titles
s clock and data recovery circuit with dual-PFD phase-rotating phase locked loop
Authors
유창식
Keywords
clock and data recovery (CDR); wireline transceiver; phase locked loop (PLL); phase rotation; CMOS
Issue Date
2014-06
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, KIKAI-SHINKO-KAIKAN BLDG, 3-5-8, SHIBA-KOEN, MINATO-KU, TOKYO, 105-0011, JAPAN
Citation
IEICE ELECTRONICS EXPRESS, 11(11), 20140351p
Abstract
A clock and data recovery (CDR) circuit for 1.5-5.0 Gb/s wireline transceiver is described. A phase locked loop (PLL) with dual phase frequency detector (PFD) and charge pump (CP) pairs performs the seamless phase rotation for the CDR circuit to track the phase and frequency difference. The CDR circuit implemented in a 65 nm CMOS process consumes 22.8 mW from a 1.2 V supply at 5.0 Gb/s. For 25 MHz jitter frequency, the CDR circuit can tolerate up to 0.21 unit-interval (UI) jitter with bit error rate (BER) smaller than 10(-12).
URI
http://www.jstage.jst.go.jp/article/elex/11/11/11_11.20140351/_article/-char/enhttp://hdl.handle.net/20.500.11754/54731
ISSN
1349-2543
DOI
http://dx.doi.org/10.1587/elex.11.20140351
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
Files in This Item:
There are no files associated with this item.
Export
RIS (EndNote)
XLS (Excel)
XML


qrcode

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

BROWSE