Electrical characterization of flash memory structure with vanadium silicide nano-particles

Abstract

We fabricated vanadium silicide (V 3 Si) nano-particles embedded in silicon dioxide dielectric layer and characterized their charging effect to apply a non-volatile memory device. To create the V 3 Si nano-particles, the first post-annealing process in N 2 gas ambient by rapid thermal annealing method was done at 800 o C for 5s. V 3 Si nano-particles with an average size of approximately 4-6nm were distributed between the tunnel and control oxide layers. The channel length and width of the transistor are 5μm. This device maintained the memory window at about 1V after 10 4 s, when applied program/erase voltages are +/-9V for 1s. This result indicates that V 3 Si nano-particles have a high potential for non-volatile memory devices.