Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 이승백 | - |
dc.date.accessioned | 2018-03-23T01:54:27Z | - |
dc.date.available | 2018-03-23T01:54:27Z | - |
dc.date.issued | 2012-12 | - |
dc.identifier.citation | Journal of Vacuum Science & Technology. B, 2012, 30(6), P.06F802 | en_US |
dc.identifier.issn | 1071-1023 | - |
dc.identifier.issn | 2166-2746 | - |
dc.identifier.uri | https://avs.scitation.org/doi/10.1116/1.4767234 | - |
dc.identifier.uri | http://hdl.handle.net/20.500.11754/51023 | - |
dc.description.abstract | The authors report on the development of a self-aligned double layer resist processing technique that allows incorporation of ion channel nanopores into on-chip microfluidic channels. The patterned positive/negative electron-beam resist double layer acts as a sacrificial template for the fabrication of on-chip fluidic channels and the nanopores. By controlling the resist dimensions, it was possible to tailor the shape of the on-chip fluidic channel and the nanopore dimensions. Using this technique, the authors demonstrated the fabrication of sub-10 nm nanopore arrays on 2 mu m wide and 800nm high on-chip fluidic channels. With further developments, it will be possible to have controllable on-chip nanopores with integrated nanofluidics. (C) 2012 American Vacuum Society. [http://dx.doi.org.access.hanyang.ac.kr/10.1116/1.4767234] | en_US |
dc.description.sponsorship | This work has been supported by the Converging Research Center Program of the Ministry of Education, Science and Technology (MEST), Korea, under the project title of "Development of Technologies for Isolation, Analysis, and Diagnosis System of Circulating Cancer Stem Cells" (Project No. 201100000001475) for the "Development of Cancer Prognosis/Diagnosis Technology based on Circulating Tumor Cell (CTC)." | en_US |
dc.language.iso | en | en_US |
dc.publisher | American Vacuum Society; 1999 | en_US |
dc.title | Fabrication of on-chip fluidic channels incorporating nanopores using self-aligned double layer resist processing technique | en_US |
dc.type | Article | en_US |
dc.relation.no | 6 | - |
dc.relation.volume | 30 | - |
dc.identifier.doi | 10.1116/1.4767234 | - |
dc.relation.page | 1-4 | - |
dc.relation.journal | JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B | - |
dc.contributor.googleauthor | Kim, Bong | - |
dc.contributor.googleauthor | Kwon, Jihun | - |
dc.contributor.googleauthor | Kim, Daehong | - |
dc.contributor.googleauthor | Chun, Sungwoo | - |
dc.contributor.googleauthor | Lee, Hyungyu | - |
dc.contributor.googleauthor | Lee, SeungBeck | - |
dc.relation.code | 2012206100 | - |
dc.sector.campus | S | - |
dc.sector.daehak | COLLEGE OF ENGINEERING[S] | - |
dc.sector.department | DEPARTMENT OF ELECTRONIC ENGINEERING | - |
dc.identifier.pid | sbl22 | - |
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