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Small-area low-ripple chopper instrumentation amplifier using sample-and-hold circuit

Title
Small-area low-ripple chopper instrumentation amplifier using sample-and-hold circuit
Author
권오경
Keywords
choppers (circuits); amplifiers; sample and hold circuits; CMOS integrated circuits; 1/f noise; integrated circuit noise
Issue Date
2013-09
Publisher
IET
Citation
Electronics letters, 2013, 49(19), P.1203-1205
Abstract
A small-area low-ripple chopper instrumentation amplifier (IA) using a sample-and-hold circuit is proposed. The proposed chopper IA employs a ripple-reduction loop (RRL) to suppress chopper ripple which is generated by the up-modulated offset and 1/f noise. The conventional RRL is not area-efficient since a sensing capacitor occupies a large chip area. Thus, the RRL using the sample-and-hold circuit to reduce the chip area is proposed. The proposed chopper IA is fabricated by using a 0.18 μm CMOS process technology and has a smaller chip area of 0.054 mm2 than that of the state-of-the-art design. The measured input-referred ripples with and without the proposed RRL are less than 3.12 mV and 67 μV, respectively.
URI
https://ieeexplore.ieee.org/document/6612781/
ISSN
0013-5194
DOI
10.1049/el.2013.1326
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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