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Capacitor-less memory cell fabricated on nano-scale strained Si on a relaxed SiGe layer-on-insulator

Title
Capacitor-less memory cell fabricated on nano-scale strained Si on a relaxed SiGe layer-on-insulator
Author
박재근
Keywords
FIELD-EFFECT TRANSISTORS; ELECTRICAL CHARACTERISTICS; MOBILITY; TRANSPORT; MOSFETS; SOI
Issue Date
2013-02
Publisher
IOP Publishing LTD
Citation
Semiconductor Science and Thechnology, Feb 2013, 28(4), P.045001
Abstract
We investigated the combined effect of the strained Si channel and hole confinement on the memory margin enhancement for a capacitor-less memory cell fabricated on nano-scale strained Si on a relaxed SiGe layer-on-insulator (epsilon-Si SGOI). The memory margin for the epsilon-Si SGOI capacitor-less memory cell was higher than that of the memory cell fabricated on an unstrained Si-on-insulator (SOI) and increased with increasing Ge concentration of the relaxed SiGe layer; i.e. the memory margin for the epsilon-Si SGOI capacitor-less memory cell (138.6 mu A) at a 32 at% Ge concentration was 3.3 times higher than the SOI capacitor-less memory cell (43 mu A).
URI
http://iopscience.iop.org/article/10.1088/0268-1242/28/4/045001/metahttp://hdl.handle.net/20.500.11754/44049
ISSN
0268-1242
DOI
10.1088/0268-1242/28/4/045001
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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