Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 권오경 | - |
dc.date.accessioned | 2018-03-09T00:41:40Z | - |
dc.date.available | 2018-03-09T00:41:40Z | - |
dc.date.issued | 2011-07 | - |
dc.identifier.citation | In: Electronics Letters. (Electronics Letters, 7 July 2011, 47(14):790-791) | en_US |
dc.identifier.issn | 0013-5194 | - |
dc.identifier.uri | http://dx.doi.org/10.1049/el.2011.1351 | - |
dc.identifier.uri | http://hdl.handle.net/20.500.11754/43869 | - |
dc.description.abstract | A 14-bit two-step successive approximation analogue-to-digital converter (SA ADC) for high-resolution CMOS imagers is proposed. The proposed SA ADC consumes a small area because it uses only a capacitor array for 7-bit resolution to implement 14-bit ADC. To enhance accuracy, it uses digital-to-analogue conversion (DAC) embedded reference buffers to calibrate reference voltages. The average switching energy in the capacitor array is only 5.8 pJ per single conversion step. The HSPICE post-layout simulation results show that SNDR of the proposed ADC is improved from 73.41 to 81.52 dB after calibration. | en_US |
dc.language.iso | en | en_US |
dc.publisher | INST ENGINEERING TECHNOLOGY-IET, MICHAEL FARADAY HOUSE SIX HILLS WAY STEVENAGE, HERTFORD SG1 2AY, ENGLAND | en_US |
dc.title | 14-bit two-step successive approximation ADC with calibration circuit for high-resolution CMOS imagers | en_US |
dc.type | Article | en_US |
dc.relation.no | 14 | - |
dc.relation.volume | 47 | - |
dc.identifier.doi | 10.1049/el.2011.1351 | - |
dc.relation.page | 790-791 | - |
dc.relation.journal | ELECTRONICS LETTERS | - |
dc.contributor.googleauthor | Shin, M-S | - |
dc.contributor.googleauthor | Kwon, O-K | - |
dc.relation.code | 2011202795 | - |
dc.sector.campus | S | - |
dc.sector.daehak | COLLEGE OF ENGINEERING[S] | - |
dc.sector.department | DEPARTMENT OF ELECTRONIC ENGINEERING | - |
dc.identifier.pid | okwon | - |
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