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dc.contributor.author권오경-
dc.date.accessioned2018-03-09T00:41:40Z-
dc.date.available2018-03-09T00:41:40Z-
dc.date.issued2011-07-
dc.identifier.citationIn: Electronics Letters. (Electronics Letters, 7 July 2011, 47(14):790-791)en_US
dc.identifier.issn0013-5194-
dc.identifier.urihttp://dx.doi.org/10.1049/el.2011.1351-
dc.identifier.urihttp://hdl.handle.net/20.500.11754/43869-
dc.description.abstractA 14-bit two-step successive approximation analogue-to-digital converter (SA ADC) for high-resolution CMOS imagers is proposed. The proposed SA ADC consumes a small area because it uses only a capacitor array for 7-bit resolution to implement 14-bit ADC. To enhance accuracy, it uses digital-to-analogue conversion (DAC) embedded reference buffers to calibrate reference voltages. The average switching energy in the capacitor array is only 5.8 pJ per single conversion step. The HSPICE post-layout simulation results show that SNDR of the proposed ADC is improved from 73.41 to 81.52 dB after calibration.en_US
dc.language.isoenen_US
dc.publisherINST ENGINEERING TECHNOLOGY-IET, MICHAEL FARADAY HOUSE SIX HILLS WAY STEVENAGE, HERTFORD SG1 2AY, ENGLANDen_US
dc.title14-bit two-step successive approximation ADC with calibration circuit for high-resolution CMOS imagersen_US
dc.typeArticleen_US
dc.relation.no14-
dc.relation.volume47-
dc.identifier.doi10.1049/el.2011.1351-
dc.relation.page790-791-
dc.relation.journalELECTRONICS LETTERS-
dc.contributor.googleauthorShin, M-S-
dc.contributor.googleauthorKwon, O-K-
dc.relation.code2011202795-
dc.sector.campusS-
dc.sector.daehakCOLLEGE OF ENGINEERING[S]-
dc.sector.departmentDEPARTMENT OF ELECTRONIC ENGINEERING-
dc.identifier.pidokwon-
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COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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