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14-bit two-step successive approximation ADC with calibration circuit for high-resolution CMOS imagers

Title
14-bit two-step successive approximation ADC with calibration circuit for high-resolution CMOS imagers
Author
권오경
Issue Date
2011-07
Publisher
INST ENGINEERING TECHNOLOGY-IET, MICHAEL FARADAY HOUSE SIX HILLS WAY STEVENAGE, HERTFORD SG1 2AY, ENGLAND
Citation
In: Electronics Letters. (Electronics Letters, 7 July 2011, 47(14):790-791)
Abstract
A 14-bit two-step successive approximation analogue-to-digital converter (SA ADC) for high-resolution CMOS imagers is proposed. The proposed SA ADC consumes a small area because it uses only a capacitor array for 7-bit resolution to implement 14-bit ADC. To enhance accuracy, it uses digital-to-analogue conversion (DAC) embedded reference buffers to calibrate reference voltages. The average switching energy in the capacitor array is only 5.8 pJ per single conversion step. The HSPICE post-layout simulation results show that SNDR of the proposed ADC is improved from 73.41 to 81.52 dB after calibration.
URI
http://dx.doi.org/10.1049/el.2011.1351http://hdl.handle.net/20.500.11754/43869
ISSN
0013-5194
DOI
10.1049/el.2011.1351
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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