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A Wear-Leveling Algorithm Exploiting k-bitwise Operations for Flash Storage Devices

Title
A Wear-Leveling Algorithm Exploiting k-bitwise Operations for Flash Storage Devices
Author
김보경
Keywords
Wear-leveling; Flash Translation Layer; Flash Storage Device; NAND Flash Memory; GARBAGE COLLECTION ALGORITHM; CONSUMER ELECTRONICS; TRANSLATION LAYER; MEMORY
Issue Date
2015-11
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation
IEEE TRANSACTIONS ON CONSUMER ELECTRONICS, v. 61, No. 4, Page. 470-477
Abstract
Flash storage devices are widely used for mobile consumer electronics due to small size, low power consumption, and high performance. Generally, the flash storage device consists of NAND flash memories. Compared to traditional magnetic disks, NAND flash memory requires an additional erase operation and its blocks have limited erase cycles. For extending its endurance, various wear-leveling algorithms have been proposed. However, they invoke many read/write/erase operations and use many memory resources for managing their block states because they do not consider the property of the flash translation layer. To solve these problems, a new wear-leveling algorithm for the log-based flash translation layer is proposed in this paper. In the log-based flash translation layer, since log blocks are frequently updated and erased, the cold block rarely removed is reserved for a next log block so that all the blocks are evenly erased. In addition, the proposed algorithm reduces the usage of memory resources by exploiting k-bitwise erase table that only needs small k-bit erase flags for managing its block erase state. Through various experiments with related wear-leveling algorithms, this paper shows the superiority of the proposed wear-leveling algorithm(1).
URI
http://ieeexplore.ieee.org/abstract/document/7389801/http://hdl.handle.net/20.500.11754/41011
ISSN
0098-3063; 1558-4127
Appears in Collections:
RESEARCH INSTITUTE[E](부설연구소) > RESEARCH INSTITUTE OF ENGINEERING & TECHNOLOGY(공학기술연구소) > Articles
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