A 10-MHz multi-bit MASH delta-sigma modulator with analog summing interstage

Title
A 10-MHz multi-bit MASH delta-sigma modulator with analog summing interstage
Author
노정진
Keywords
Delta-sigma modulator; Oversampling; Analog circuits; DESIGN; ADC
Issue Date
2015-10
Publisher
SPRINGER
Citation
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, v. 85, No. 1, Page. 201-207
Abstract
This paper presents an improved 4-bit two-stage multi-stage noise shaping (MASH) delta-sigma modulator (DSM). The two-stage MASH DSM utilizes the second-order chain of cascade of integrators with feedforward (CIFF) and the cascade of integrators with distributed feedback (CIFB) architectures for the first and second stages, respectively. The 4-bit CIFF requires an active adder, which is conventionally implemented with a high-bandwidth high-swing amplifier. In the proposed DSM, the active adder is eliminated and the adder-less integrator is applied in the first stage of the MASH DSM. The first stage quantization noise, which is fed to the second stage, is conventionally extracted from the analog input and digital output of the quantizer in the first stage. The number of quantizer digital output paths increases exponentially with the quantization bit number. A large number of DAC feedback paths in the interstage is avoided by proposing a new interstage topology based on analog summing to derive the first stage quantization noise in the analog domain. The prototype DSM is fabricated in a 0.11-m CMOS process. When operating from a 1.2-V supply, the modulator achieves 67.8-dB peak SNDR, while consuming 25 mW, with an OSR of 8 at a 160-MHz sampling frequency.
URI
https://link.springer.com/article/10.1007%2Fs10470-015-0609-9http://hdl.handle.net/20.500.11754/40266
ISSN
0925-1030; 1573-1979
DOI
10.1007/s10470-015-0609-9
Appears in Collections:
COLLEGE OF ENGINEERING SCIENCES[E](공학대학) > ELECTRICAL ENGINEERING(전자공학부) > Articles
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