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Efficiency optimization of charge pump circuit in NAND FLASH memory

Title
Efficiency optimization of charge pump circuit in NAND FLASH memory
Author
박재근
Keywords
NAND FLASH; charge pump; efficiency; current reduction
Issue Date
2011-08
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, KIKAI-SHINKO-KAIKAN BLDG, 3-5-8, SHIBA-KOEN, MINATO-KU, TOKYO, 105-0011, JAPAN
Citation
IEICE Electronics Express, Vol.8 No.16 [2011], 1343-1347
Abstract
In this paper, power efficiency optimization scheme of charge pump circuit in NAND FLASH memory was proposed. The proposed scheme was implemented in program/erase charge pump by pump stage number control method. The maximum power efficiency of this pump is about 30%, and the maximum point is around 70% point of highest voltage level. So in this paper, to operate program/erase pump in highest power efficiency area, the pump stage number control scheme is proposed and evaluated in 20nm 64Gb MLC NAND FLASH memory circuit. Simulation result shows overall improvement of power efficiency, and at the wafer test about 10mA peak current reduction and overall improvement of power dissipation are found.
URI
https://www.jstage.jst.go.jp/article/elex/8/16/8_16_1343/_article
ISSN
1349-2543
DOI
10.1587/elex.8.1343
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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