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A multi-level capacitor-less memory cell fabricated on a nano-scale strained silicon-on-insulator

Title
A multi-level capacitor-less memory cell fabricated on a nano-scale strained silicon-on-insulator
Author
박재근
Issue Date
2011-07
Publisher
IOP Publishing LTD
Citation
Nanotechnology, 2011, 22(31), 315201
Abstract
A multi-level capacitor-less memory cell was fabricated with a fully depleted n-metal-oxide-semiconductor field-effect transistor on a nano-scale strained silicon channel on insulator (FD sSOI n-MOSFET). The 0.73% biaxial tensile strain in the silicon channel of the FD sSOI n-MOSFET enhanced the effective electron mobility to similar to 1.7 times that with an unstrained silicon channel. This thereby enables both front-and back-gate cell operations, demonstrating eight-level volatile memory-cell operation with a 1 ms retention time and 12 mu A memory margin. This is a step toward achieving a terabit volatile memory cell.
URI
http://www.ndsl.kr/ndsl/search/detail/article/articleSearchResultDetail.do?cn=NART64142714
ISSN
0957-4484
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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