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Reliability Degeneration Mechanisms of the 20-nm Flash Memories Due to the Word Line Stress

Title
Reliability Degeneration Mechanisms of the 20-nm Flash Memories Due to the Word Line Stress
Author
김태환
Keywords
NAND Flash Memory; Word Line Stress; Degeneration Mechanism; Program/Erase Cycle
Issue Date
2016-02
Publisher
AMER SCIENTIFIC PUBLISHERS
Citation
JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, v. 16, NO 2, Page. 1669-1671
Abstract
The electrical characteristics of NAND flash memories with a high-k dielectric layer were simulated by using a full three-dimensional technology computer-aided design simulator. The occurrence rate of the errors in the flash memories increases with increasing program/erase cycles. To verify the word line stress effect, electron density in the floating gate of target cell and non-target cell, the drain current in the channel of non-target cell and depletion region of the non-target cell were simulated as a function of program/erase cycle, for various floating gate thicknesses. The electron density in the floating gate became decreased with increasing program/erase cycles. The reliability degradation occured by the increased depletion region at the bottom of the polysilicon floating gate in the continued program/erase cycle situation due to the word line stress. The degradation mechanisms for the program characteristics of 20-nm NAND flash memories were clarified by examining electron density, darin current and depletion region.
URI
http://www.ingentaconnect.com/content/asp/jnn/2016/00000016/00000002/art00072;jsessionid=2gt1emf445t6c.x-ic-live-02http://hdl.handle.net/20.500.11754/34071
ISSN
1533-4880; 1533-4899
DOI
10.1166/jnn.2016.11950
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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