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A Low-Noise and Area-Efficient PWM-Delta Sigma ADC Using a Single-Slope Quantizer for CMOS Image Sensors

Title
A Low-Noise and Area-Efficient PWM-Delta Sigma ADC Using a Single-Slope Quantizer for CMOS Image Sensors
Author
권오경
Keywords
CMOS image sensor (CIS); column-parallel readout; delta-sigma (Delta Sigma) analog-to-digital converter (ADC); single-slope (SS) quantizer
Issue Date
2016-01
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation
IEEE TRANSACTIONS ON ELECTRON DEVICES, v. 63, Page. 168-173
Abstract
This paper proposes a multibit pulsewidth modulated (PWM) delta-sigma (Delta Sigma) analog-to-digital converter (ADC) using a single-slope (SS) quantizer for a CMOS image sensor (CIS). In the proposed ADC, the multibit Delta Sigma modulation is performed by converting the pulsewidth of the PWM signal into multibit data using an SS quantizer. This suppresses the random noise by the multisampling operation and reduces the area of the multibit Delta Sigma ADC by adding a ramp signal to a single-bit Delta Sigma ADC. The proposed ADC with 12-b resolution was fabricated using a 0.13-mu m CIS process with a pixel array which has a Bayer patterned color filter and an image format of 580 x 450 with a pixel size of 5 mu m x 5 mu m. The size of the test chip is 4 mm x 5 mm, including the area of the proposed channel ADC, which occupies only 10 mu m x 400 mu m per channel. The measured results show a random noise of 65 mu V and a dynamic range of 70.4 dB.
URI
http://ieeexplore.ieee.org/document/7112101/http://hdl.handle.net/20.500.11754/30654
ISSN
0018-9383; 1557-9646
DOI
10.1109/TED.2015.2430846
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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