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A Multi-Bit Incremental ADC Based on Successive Approximation for Low Noise and High Resolution Column-Parallel Readout Circuits

Title
A Multi-Bit Incremental ADC Based on Successive Approximation for Low Noise and High Resolution Column-Parallel Readout Circuits
Author
권오경
Keywords
Column-parallel readout; incremental analog-to-digital converter (ADC); successive approximation
Issue Date
2015-09
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v. 62, NO 9, Page. 2156-2166
Abstract
This paper proposes a multi-bit incremental analog-to-digital converter (ADC) based on successive approximation (SA) for column-parallel readout circuits. The proposed ADC suppresses the random noise and enhances the resolution by embedding the conventional SA ADC with an integrator and decimation filter. In addition, the operating speed is increased through the two-step operations of coarse conversion with the proposed ADC and fine conversion with the embedded SA ADC. A residue fitting method is adopted to adjust the residue voltage to the fine conversion range after the coarse conversion. The proposed ADC with 12-bit resolution was fabricated using a 0.13 CMOS image sensor process with a pixel array that has an image format of 648 x 488 and a pixel size of 5.6 mu m x 5.6 mu m. The measured results show a random noise of 108 mu V a dynamic range of 60.9 dB, a differential nonlinearity of +1.02/-0.34 least significant bit (LSB), and an integral nonlinearity of +0.64/-0.54 LSB.
URI
http://ieeexplore.ieee.org/abstract/document/7210229/http://hdl.handle.net/20.500.11754/27613
ISSN
1549-8328; 1558-0806
DOI
10.1109/TCSI.2015.2451811
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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