Toward Zero Bit-Error-Rate Physical Unclonable Function: Mismatch-Based vs. Physical-Based Approaches in Standard CMOS Technology

Abstract

This paper compares two types of physical unclonable function (PUF) circuits in terms of reliability, mismatch-based PUF vs. physical-based PUF. Most previous PUF circuits utilize device mismatches for generating random responses. Although they have sufficient random features, there is a reliability issue that some portions of bits are changed over time during operation or under noisy environments. To overcome this issue, we previously proposed the differential amplifier PUF (DA-PUF) which improves the reliability by amplifying the small mismatches of the transistors and rejecting the power supply noise through differential operation. In this paper, we first report the experimental results with the fabricated chips in a 0.35 µm CMOS process. The DA-PUF shows 51.30% uniformity, 50.05% uniqueness, and 0.43% maximum BER. For 0% BER, we proposed the physical-based VIA-PUF which is based on the probability of physical connection between the electrical layers. From the experimental results with the fabricated chips in a 0.18 µm CMOS process, we found the VIA-PUF has 51.12% uniformity and 49.64% uniqueness, and 0% BER throughout 1,000-time repeated measurements. Especially, we have no bit change after the stress test at 25 and 125 °C for 96 hours.