A 6-Gbps/lane receiver for a clock-forwarded link in 65-nm CMOS process

Title
A 6-Gbps/lane receiver for a clock-forwarded link in 65-nm CMOS process
Authors
유창식
Keywords
CMOS; clock and data recovery; CDR; phase locked loop; PLL; decision feedback equalizer; DFE; clock forwarded link
Issue Date
2015-04
Publisher
WILEY-BLACKWELL
Citation
INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, v. 43, NO 4, Page. 544-552
Abstract
For a 6-Gbps/lane clock-forwarded link, a wireline receiver has been developed. The phases of the sampling clocks are aligned to the center of the input data eye by a clock and data recovery (CDR) circuit. In the CDR circuit, the sampling clock phases are rotated by a phase rotating phase locked loop (PLL). A three-tap decision feedback equalizer (DFE) compensates for the loss of cable together with a continuous-time linear equalizer (CTLE) to ensure sufficient eye opening for the CDR circuit to find the optimum sampling phase. The DFE coefficients are adaptively calculated based on the data and edge samples. Implemented in a 65-nm CMOS process, the three-lane 6-Gbps/lane receiver for a clock-forwarded link occupies 0.63mm(2) including pads and consumes 288mA from a 1.2-V supply. Copyright (c) 2015 John Wiley Sons, Ltd.
URI
http://onlinelibrary.wiley.com/doi/10.1002/cta.2080/abstract;jsessionid=C1CF9FB522A84DB22B35B519ECF36EF1.f03t04http://hdl.handle.net/20.500.11754/24116
ISSN
0098-9886; 1097-007X
DOI
http://dx.doi.org/10.1002/cta.2080
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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