Design Tradeoffs of SSDs: From Energy Consumption's Perspective

Title
Design Tradeoffs of SSDs: From Energy Consumption's Perspective
Authors
원유집
Keywords
Design; Measurement; SSD; NAND flash; energy consumption; FTL; parallelism; simulator
Issue Date
2015-03
Publisher
ASSOC COMPUTING MACHINERY
Citation
ACM TRANSACTIONS ON STORAGE, v. 11, NO 2, Page. 1-24
Abstract
In this work, we studied the energy consumption characteristics of various SSD design parameters. We developed an accurate energy consumption model for SSDs that computes aggregate, as well as component-specific, energy consumption of SSDs in sub-msec time scale. In our study, we used five different FTLs (page mapping, DFTL, block mapping, and two different hybrid mappings) and four different channel configurations (two, four, eight, and 16 channels) under seven different workloads (from large-scale enterprise systems to small-scale desktop applications) in a combinatorial manner. For each combination of the aforementioned parameters, we examined the energy consumption for individual hardware components of an SSD (micro-controller, DRAM, NAND flash, and host interface). The following are some of our findings. First, DFTL is the most energy-efficient address-mapping scheme among the five FTLs we tested due to its good write amplification and small DRAM footprint. Second, a significant fraction of energy is being consumed by idle flash chips waiting for the completion of NAND operations in the other channels. FTL should be designed to fully exploit the internal parallelism so that energy consumption by idle chips is minimized. Third, as a means to increase the internal parallelism, increasing way parallelism (the number of flash chips in a channel) is more effective than increasing channel parallelism in terms of peak energy consumption, performance, and hardware complexity. Fourth, in designing high-performance and energy-efficient SSDs, channel switching delay, way switching delay, and page write latency need to be incorporated in an integrated manner to determine the optimal configuration of internal parallelism.
URI
http://dl.acm.org/citation.cfm?id=2644818http://hdl.handle.net/20.500.11754/23299
ISSN
1553-3077; 1553-3093
DOI
http://dx.doi.org/10.1145/2644818
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > DIVISION OF COMPUTER SCIENCES AND ENGINEERING(컴퓨터공학부) > Articles
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