A Low-Power CMOS Image Sensor With Area-Efficient 14-bit Two-Step SA ADCs Using Pseudomultiple Sampling Method

Title
A Low-Power CMOS Image Sensor With Area-Efficient 14-bit Two-Step SA ADCs Using Pseudomultiple Sampling Method
Authors
권오경
Keywords
Column-parallel analog-to-digital (A/D) converter (ADC); digital correlated double sampling (CDS); pseudomultiple sampling (PMS); successive approximation (SA) ADC; small area
Issue Date
2015-03
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v. 62, NO 5, Page. 451-455
Abstract
This brief presents a low-power CMOS image sensor with 14-bit column-parallel two-step (TS) successive approximation (SA) analog-to-digital converters (ADCs). The proposed TS SA ADC adopts a pseudomultiple sampling method to reduce the power consumption and the area. For implementing the 14-bit ADC, it only uses a capacitor digital-to-analog converter of 6 bits rather than 14 bits. The multiple sampling also suppresses the noise of a pixel and a column-parallel ADC. The image sensor is fabricated by using the 0.13-mu m CMOS process. The measurement results show that the temporal noise is 82.7 mu V-rms, and the power consumption is 55.1 mu W for one column ADC with a programmable gain amplifier. With the digital correlated double sampling and the TS calibration method, the proposed ADC achieves the column fixed-pattern noise of 0.98 LSB and a differential non-linearity of +0.99/-0.90 LSB.
URI
http://ieeexplore.ieee.org/document/7001248/?arnumber=7001248&tag=1http://hdl.handle.net/20.500.11754/22982
ISSN
1549-7747; 1558-3791
DOI
http://dx.doi.org/10.1109/TCSII.2014.2387531
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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