Data loss recovery for power failure in flash memory storage systems

Title
Data loss recovery for power failure in flash memory storage systems
Authors
송용호
Keywords
Power failure; Power loss recovery; Storage management; Flash storage system
Issue Date
2015-01
Publisher
ELSEVIER SCIENCE BV
Citation
JOURNAL OF SYSTEMS ARCHITECTURE, v. 61, NO 1, Page. 12-27
Abstract
Due to the rapid development of flash memory technology, NAND flash has been widely used as a storage device in portable embedded systems, personal computers, and enterprise systems. However, flash memory is prone to performance degradation due to the long latency in flash program operations and flash erasure operations. One common technique for hiding long program latency is to use a temporal buffer to hold write data. Although DRAM is often used to implement the buffer because of its high performance and low bit cost, it is volatile; thus, that the data may be lost on power failure in the storage system. As a solution to this issue, recent operating systems frequently issue flush commands to force storage devices to permanently move data from the buffer into the non-volatile area. However, the excessive use of flush commands may worsen the write performance of the storage systems. In this paper, we propose two data loss recovery techniques that require fewer write operations to flash memory. These techniques remove unnecessary flash writes by storing storage metadata along with user data simultaneously by utilizing the spare area associated with each data page.
URI
http://hdl.handle.net/20.500.11754/21683http://www.sciencedirect.com/science/article/pii/S138376211400143X
ISSN
1383-7621
DOI
http://dx.doi.org/10.1016/j.sysarc.2014.11.002
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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