A STUDY OF BCDU AND LWR IMPROVEMNETS VIA ATOMIC LAYER DEPOSITON

Abstract

A study of BCDU and LWR improvements via Atomic Layer Deposition Yonghoon Seo Dept. of Material Science & Eng. The Graduate School Hanyang University Recently, in order to increase semiconductor integration, many semiconductor manufacturers are using a method of reducing the line width. Manufacturers use optical double patterning trench (DPT) and quadruple patterning trench (QPT) with immersion lithography (λ = 193 nm), but these techniques may soon reach their limits. Extreme ultraviolet lithography (EUV, λ = 13.5 nm) is expected to be the next-generation lithography technique for making electronic circuits cost-effectively at the sub-20 nm node. EUV has allowed a drastic improvement of the lithographic resolution. However, line edge/width roughness (LER/LWR) is being recognized as a major concern in device manufacturing. More specifically, it is strongly associated with the deterioration of the block critical dimension (CD) uniformity if the roughness of mesh pattern created by two EUV line patterns is not controlled. In this study, we performed ALD using a BTBAS (Bis(tertiarybutylamino) Silane) precursor that is sufficiently reactive at room temperature. This process produced a SiO2 layer, and we wanted to overcome the patterning problem by supporting the EUV photo resist (PR) without collapsing. The result of BTBAS deposition improves BCDU ~40% from Pre (BCDU ~0.8nm improvement and LWR ~0.3nm improvement) than non BTBAS deposition. It has successfully demonstrated BTBAS deposition feasibility for BCDU, LWR, high selectivity improvement in process chamber.