Research on Ultra-Low Power PMIC Designs of Buck Converter and High PSRR LDO

Abstract

With the development of the Internet of Things (IoT), low-power devices are becoming increasingly important in areas such as healthcare, smart home automation, wearable devices, and industrial instruments. To facilitate the use of such products, it is necessary to achieve longer battery life and application run time. High performance power management integrated chips (PMICs) that can maximize battery life and reduce standby power consumption are becoming increasingly important. In this dissertation, ultra-low power PMICs that including the low drop-out (LDO) regulator and DC–DC converter are presented. The first research presents a high power supply rejection ratio (PSRR) LDO regulator with a low quiescent current. A low quiescent current capacitive feed-forward ripple cancellation (CFFRC) technique is proposed to cancel the power supply noise. With this technique, low power consumption is achieved via the feed-forward capacitors and the back-to-back pseudo-resistors bias. This design was fabricated using 0.18-µm CMOS technology. The entire proposed LDO consumes a quiescent current of 0.9 µA. Compared to an LDO without the enhancement, at the maximum load current of 200 mA, the measured PSRR has an enhancement of -22 dB at 1 MHz. The second research presents a low-quiescent current, high-efficiency Buck converter. A dynamic pulse width modulation (PFM) control with adaptive off-time is proposed to increase efficiency. An ultra-low power system can be achieved with minimized quiescent current in each block and a low-power bandgap reference (BGR). The entire proposed Buck converter consumes a quiescent current of 464 nA with a peak efficiency of 93.7% over the load range from 0 to 50 mA. In addition, a maximum converter output ripple of only 28 mV is achieved at this ultra-low quiescent current.