Research on Low-Power and High-Performance LDO Regulators for IoT Applications

Abstract

Recently, various features such as improvements in AP (Application Processor) performance, advancements in internal camera technology, and increased memory have been developed, leading to significant enhancements in the battery-operated Internet of Things (IoT) applications. However, with the development of these features, the power consumption of mobile devices is also increasing. To minimize the power used by IoT applications, the need for research on efficient Power Management Integrated Circuits (PMIC) has been consistently important. In this paper, this research focuses on research to address the requirements of these PMIC markets. The first research introduces a low-dropout regulator (LDO) designed for powerefficient battery-operated IoT devices. When IoT devices enter low-power standby mode, this novel LDO is capable of detecting the load current and transitioning into an ultra-low-power state, thereby enabling an energy-efficient system. This proposed LDO operates by switching between two distinct modes. The first is an ultra-low-power mode, during which the LDO’s core circuit is deactivated to conserve power. The second is an active mode where all circuit components are engaged. The effectiveness of this approach has been validated through the development and measurement of silicon LDO chips, which exhibit an impressively low quiescent current of 13.5 nA and a superior Figure-of-Merit (FOM). The second research addresses the issue of non-ideal virtual ground at the feedback node of an LDO regulator, which utilizes an off-chip capacitor employing a negative-R-assisted technique. This technique enhances the LDO’s overall performance, particularly in terms of load/line regulation and power supply rejection (PSR). By employing this approach, the LDO is capable of achieving enhanced performance despite the relatively small size of the pass transistor, resulting in the LDO regulators that are both power-efficient and compact in terms of silicon area. The proposed negativeR-assisted LDO is capable of a load current of 100 mA, with a load regulation of 0.09 mV/mA, a line regulation of 6 mV/V, and a PSR of -31 dB. The implementation of this negative-R-assisted LDO was implemented with 150 nm transistors in a 28 nm standard CMOS process, with an active area of 4,200 µm². Furthermore, the proposed LDO achieves a superior figure-of-merit (FoM) with values of 13.5 ps (FoM1) and 0.057 ps·mm² (FoM2).