A comprehensive TCAD study of individual traps with the proposal of energy diagnosis and mitigation of its effects in n-MOSFETs.

Abstract

Metal oxide field-effect transistor (MOSFET) is a critical component in almost every electronic device. Most power failures (over 34%) in electronic devices are due to the failure of MOSFETs. To mitigate the effect of failure-causing factors, the first prime step is to diagnose the cause of failure. The presence of traps at the Si/SiO2 interface or Si substrate in MOSFET devices is one of the foremost factors which drastically affect its operation. Traps being a big source of variability, cause the mismatch of transistors’ performance and leads to failure. To have a comprehensive view of individual traps, variable trap locations are considered on Si/SiO2 interface and Si substrate. Each trap location is filled with a trap alternatively and simulated via Sentaurus TCAD at multiple energy levels between mid-band to conduction band. The electron charge pumping cycle is recorded to understand each trap's dynamics. In this study, electron charge emission in low time, contributing to substrate current is considered as an indicator to estimate degradation in device performance. The specific value of charge emission in low time contributing to substrate current from an individual-specified trap (an individual localized trap at a specific energy level), reveals the impact of that trap on device degradation. A special case is also discussed to calculate the threshold of failure time based on the accumulation of one femtocoulomb charge in the low time. For the identification and verification of the degradation contributing trap’s energy, different switching transients (waveforms) have been proposed in this work. Herein, using a conventional square waveform, a single eNeutral trap is simulated at a distribution of energy levels to identify the trap’s energy that emit in the low time. These are the traps that contribute to device degradation. The energy of a specific trap that plays a vital role in device degradation is also identified. Based on the results, two waveforms are proposed by manipulating the speed and fall time to exploit the trap emission during n-MOSFET off time. The proposed waveforms omit or reduce the probability of failure and verify the energy of DC Traps. A comparison of results from all three waveforms verifies the energy of DC traps with high resolution. For the application of this work, an experiment was performed, in which the leakage path of individual tail cells in 2x nm technology DDR4 DRAM at operating temperature was revealed. For leakage path determination activation energy (Ea) was used as a tool through its extraction by retention time measurement. Retention testing was performed at operating temperature on selected 0.07 ppm retention tail cells that concludes gate-induced drain leakage (GIDL) is the dominant leakage path in this device. Correlation between Ea and retention time measured at operating temperature (40 °C, 60 °C, or 80 °C) explored the leakage mechanisms corresponding to Ea of the extracted dominant leakage path (GIDL). These failure leakage mechanisms, dominating on certain values of operating temperature are divulged as the root cause of failure at that temperature.