Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 박성주 | - |
dc.date.accessioned | 2021-04-26T04:55:06Z | - |
dc.date.available | 2021-04-26T04:55:06Z | - |
dc.date.issued | 2000-05 | - |
dc.identifier.citation | 2000 IEEE International Symposium on Circuits and Systems (ISCAS), v. 1, page. 88-91 | en_US |
dc.identifier.uri | https://ieeexplore.ieee.org/document/857033?arnumber=857033&SID=EBSCO:edseee | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/161695 | - |
dc.description.abstract | To overcome the large extra hardware overhead attendant in the full scan design, the concept of partial scan designs has emerged with the virtue of less area and testability close to full scan. In this paper we analyzed and unified the strength of the techniques by structural analysis and testabilities. The new partial scan design proposed not only reduces the time for selecting scan flip-flops but also preserves high fault coverage. Test results demonstrate the high fault coverage and remarkable reduction in time for the most ISCAS89 benchmark circuits. | en_US |
dc.language.iso | en_US | en_US |
dc.publisher | IEEE | en_US |
dc.title | A Partial Scan Design by Unifying Structural Analysis and Testabilities | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/ISCAS.2000.857033 | - |
dc.relation.journal | 국제Proceeding(기타) | - |
dc.contributor.googleauthor | Shin, S | - |
dc.contributor.googleauthor | Park, S | - |
dc.contributor.googleauthor | Park, J | - |
dc.relation.code | 2012101922 | - |
dc.sector.campus | E | - |
dc.sector.daehak | COLLEGE OF COMPUTING[E] | - |
dc.sector.department | DIVISION OF COMPUTER SCIENCE | - |
dc.identifier.pid | paksj | - |
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