Design of Two-bit NAND SONOS Memory Devices Utilizing the Tunneling Oxide Thickness Difference

Abstract

Not AND (NAND) silicon-oxide-nitride-oxide-silicon (SONOS) memory devices with the different tunneling oxide thickness are proposed to reduce short-channel effect (SCE) and coupling interference. In addition, the proposed SONOS memory devices are suggested to achieve fast program and erase speed and increase the memory density in comparison with conventional non volatile memory (NVM). The proposed SONOS memory devices are simulated by using the SUPREM-4 to study the process step and using the MEDICI to analysis the electrical characteristics. The program and the erase processes of the proposed SONOS memory devices are simulated by using the Fowler-Nordheim (FN) tunneling mechanism. The electrical characteristics of the NAND SONOS memory devices with different tunneling oxide thickness were better than those of the conventional NAND SONOS devices. Simulation results showed that the decrease of SCE and coupling interference for the proposed SONOS devices was achieved by fabricating asymmetric source/drain (S/D) and making the tunneling oxide thickness difference in the gate1 and gate2. These results indicate that NAND SONOS memory devices with different tunneling oxide thickness provide potential applications in scaling-down and high-efficiency nonvolatile memory devices.