DisplayPort를 위한 기준 클럭이 필요 없는 클럭 및 데이터 복원 기법

Abstract

This dissertation presents the design of a clock and data recovery circuit for DispayPort Ver. 1.1. DisplayPort is a next generation digital display interface standard specified by VESA (Video Electronics Standard Association) with optional audio and content protection capability for broad application within PC and consumer electronics devices. The clock and data recovery (CDR) for the physical layer of DisplayPort at sink side is designed. A 1/5-rate linear phase detector (PD) compares the phase of the incoming data with that of sampling clock to recover a clean clock and data. A pattern based frequency detector (PBFD) reduces frequency error to be in the pull-in-range of the 1/5-rate linear PD. The PBFD reduces the frequency error down to 3.2% before the linear PD starts its operation. The CDR implemented in a 0.13-um CMOS process shows 29-ps rms and 154-ps peak-to-peak jitter in the recovered clock and 10-7 bit error rate (BER) for 231-1 pseudorandom binary-sequence (PRBS) input while consuming 87mW from a 1.2-V supply.