고종횡비 비아 상의 Mo 및 Cu 씨드레이어 형성을 위한 경사 스퍼터링 연구

Abstract

시스템 인 패키지 (SIP)는 내부적으로 미세 전극으로 연결되어 있는 하나의 모듈 안에 내장된 수많은 집적 회로 (IC) 이다. 특히 3D ICs는 through-silicon-vias (TSV)에 의해 상호 연결되는 IC들을 포함한다. 이 3D ICs 기술은 무어의 법칙을 계속 적용 가능하게 하고, CMOS 소자의 크기 감소의 한계를 극복하게 한다. 또한, 3D 시스템 통합 기술은 form factor 를 줄이고 회로간의 상호연결 밀도를 증가시켜, 소비 전력을 줄이면서도 칩 속도를 증가시킨다. 현재 집적밀도를 더 높이기 위해 TSV의 고종횡비를 증가시키고자 하는 노력이 지속적으로 수행되고 있다. 일반적인 스퍼터링 방법은 직선적인 증착방식이므로 원하는 두께만큼 두껍게 좁은 비아내부에 씨드층을 형성하기 어렵다. 따라서 원자층 증착 (ALD)이나 이온화 PVD (IPVD) 같은 방식이 고품질의 씨드층 제작을 위해 제안되기도 한다. 그러나 이러한 방법은 생산원가가 높고 생산성이 떨어지므로 본 연구에서는 기존의 스퍼터링 방법을 이용하여 10:1 고종횡비 TSV의 씨드층을 효율적으로 형성할 수 있기 위한 스퍼터링 조건의 영향을 살펴보았다. 본 연구에서는 우수한 전기전도도와 Si과 Cu 중간의 열팽창계수를 갖는 Mo 버퍼층을 Cu 보다 먼저 증착하였다. 이는 Mo 버퍼층이 Cu 확산방지막과 밀착촉진막으로 작용하도록 하여 보다 우수한 Cu 씨드층을 형성하도록 하였다. 균질한 Mo 씨드층을 얻기 위하여 Mo 스퍼터링시에 스퍼터링 조건과 기판 기울임 (Tilting)을 변경하여 이에 대한 효과를 확인하였다. Cu 스퍼터링 조건 중 압력 별 비저항 특성을 살펴본 결과, 3 mTorr 이하의 낮은 압력에서 우수한 품질의 Cu 씨드층을 형성할 수 있었다. 이는 낮은 스퍼터링 압력에서는 입자산란을 줄여 직선방향 증착을 늘일 수 있어 보다 균질한 씨드층을 형성할 수 있기 때문으로 판단된다. Mo/Cu 씨드층 형성 실험을 통해 낮은 스퍼터링 파워와 짧은 스퍼터링 시간이 큰 via opening percentage를 얻기에 적합하나 충분한 하부 씨드층 두께를 얻기 위해 각 공정 변수와 제어인자 조건들이 조절되어야 함을 확인하였다. 금속 씨드층 스퍼터링 후 전기도금에 의해 구리 충진을 시도하였다. 비아의 고종횡비가 증가하면 비아 폭이 좁아져 비아의 하부층과 하단 측면 두께는 비아 상부 측면 두께만큼 충분하지 않을 경우 비아 전체적으로 구리가 충진되지 못하고 구리 도금으로 인한 충진시 상단부위에서 비아의 구멍이 막히는 문제가 발생할 수 있다. 따라서 via opening percentage을 높이기 위한 tilting 스퍼터링 방식과 동시에 씨드층의 특성을 높이기 위한 공정조건을 최적화하였다. 그 결과 입구의 opening percentage를 약 64%로 하고, 하부 씨드층 두께가 46.7 nm 인 금속 씨드층을 형성하고, 이 씨드층 상에 7.5 mA/cm2, 2 시간의 Cu 전기도금 조건으로 결함 없는 Cu filling을 성공적으로 할 수 있었다. 또한 Mo 단일막을 이용하여 Cu 확산방지막과 씨드층의 역할을 동시에 한 시편의 경우도 효과적으로 Cu 전기도금을 통한 충진을 할 수 있었다. 본 결과를 얻기 위하여 실험계획법에 의한 씨드층 스퍼터링 실험을 통하여 씨드층의 특성을 더욱 향상시키며, 기존의 종래 방식의 스퍼터링에서 tilting 방법과 공정변수 제어하여. 양산성과 경제성을 동시에 갖춘 씨드층을 형성할 수 있는 방법을 확인하였다.|A system-in-package (SiP) is a number of integrated circuits (ICs) enclosed in a single module that are internally connected by fine electrodes. In particular, 3D ICs involve interconnected ICs as they contact each other by means of through-silicon-vias (TSVs). This 3D ICs technology enables Moore’s Law to continue to apply and overcomes the lower limit of CMOS element size reduction. In addition, the 3D system integration technology reduces the form factor and increases the circuit-to-circuit interconnect density, which increases the chip speed while reducing the power consumption. Currently, it has been strongly required to increase the aspect ratio of TSVs for higher packing density. However, seed layers could not be successfully deposited as much as a desired thickness by a common sputtering technology. Atomic layer deposition (ALD) or ionized PVD (IPVD) methods should be recommended to obtain high quality seed layers. Although it is a cheap process and suitable to mass production, the conventional sputtering method has not been widely used to fabricate high aspect ratio vias due to its more or less rectilinear propagation property. In this study, the effect of sputtering conditions on the growth mechanism of seed layers was investigated to fabricate 10:1 high aspect ratio TSVs through the conventional sputtering method. In order to improve the quality of Cu seed layers, a Mo buffer layer was pre-deposited because Mo has a good conductivity and an intermediate thermal expansion coefficient between Si and Cu and the buffer layer can act as a Cu diffusion barrier and adhesive layer. In addition, it was found that a Mo single layer itself acts as a diffusion barrier and seed layer at the same time. To obtain a homogeneous and continuous Mo layer on TSV, the effect of sputtering conditions and substrate tilting was examined. In the Cu sputtering conditions, Cu seed layers with low electrical resistivity of 2.25 µΩ cm were obtained when the working pressure was maintained below 3 mTorr. This indicates that low sputtering pressure should reduce the scattering chance of Cu and Ar gas and then enhance the rectilinear propagation. For the formation of Mo/Cu seed layers, low sputtering power and short sputtering process time were desirable to obtain the high opening percentage. However, the sputtering time should be controlled to obtain a reasonable bottom seed layer thickness. In this research, metal (Mo/Cu) seed layers were deposited by a conventional sputtering method and then copper filling by electroplating was followed in order to fabricate through silicon vias with a high aspect ratio of 10:1. With increasing the aspect ratio, it becomes critical to control the reduction of via’s hole size before filling the bottom seed layer. By changing sputtering time, pressure, and power, changes in the thickness of the metal seed layers were investigated. It was found that optimizing the sputtering conditions improved the quality of the seed layer and retarded the speed of the hole size reduction. As a result, a metal seed layer with a via’s opening percentage of about 62% and a bottom seed layer thickness of 46.7 nm was fabricated by conventional sputtering using a tilting method. Using this seed layer, Cu was fully filled up in the vias after Cu electroplating in the condition of 7.5 mA/cm2 for 2 hours. Through Design of Experiments (DOE) the sputtering experiments for seed layers met the prerequisite of Cu filling electroplating. Furthermore the quality of seed layer was found to be improved. Therefore, the tilting sputtering method suggested in this experiment is suitable to an economical mass production method.; A system-in-package (SiP) is a number of integrated circuits (ICs) enclosed in a single module that are internally connected by fine electrodes. In particular, 3D ICs involve interconnected ICs as they contact each other by means of through-silicon-vias (TSVs). This 3D ICs technology enables Moore’s Law to continue to apply and overcomes the lower limit of CMOS element size reduction. In addition, the 3D system integration technology reduces the form factor and increases the circuit-to-circuit interconnect density, which increases the chip speed while reducing the power consumption. Currently, it has been strongly required to increase the aspect ratio of TSVs for higher packing density. However, seed layers could not be successfully deposited as much as a desired thickness by a common sputtering technology. Atomic layer deposition (ALD) or ionized PVD (IPVD) methods should be recommended to obtain high quality seed layers. Although it is a cheap process and suitable to mass production, the conventional sputtering method has not been widely used to fabricate high aspect ratio vias due to its more or less rectilinear propagation property. In this study, the effect of sputtering conditions on the growth mechanism of seed layers was investigated to fabricate 10:1 high aspect ratio TSVs through the conventional sputtering method. In order to improve the quality of Cu seed layers, a Mo buffer layer was pre-deposited because Mo has a good conductivity and an intermediate thermal expansion coefficient between Si and Cu and the buffer layer can act as a Cu diffusion barrier and adhesive layer. In addition, it was found that a Mo single layer itself acts as a diffusion barrier and seed layer at the same time. To obtain a homogeneous and continuous Mo layer on TSV, the effect of sputtering conditions and substrate tilting was examined. In the Cu sputtering conditions, Cu seed layers with low electrical resistivity of 2.25 µΩ cm were obtained when the working pressure was maintained below 3 mTorr. This indicates that low sputtering pressure should reduce the scattering chance of Cu and Ar gas and then enhance the rectilinear propagation. For the formation of Mo/Cu seed layers, low sputtering power and short sputtering process time were desirable to obtain the high opening percentage. However, the sputtering time should be controlled to obtain a reasonable bottom seed layer thickness. In this research, metal (Mo/Cu) seed layers were deposited by a conventional sputtering method and then copper filling by electroplating was followed in order to fabricate through silicon vias with a high aspect ratio of 10:1. With increasing the aspect ratio, it becomes critical to control the reduction of via’s hole size before filling the bottom seed layer. By changing sputtering time, pressure, and power, changes in the thickness of the metal seed layers were investigated. It was found that optimizing the sputtering conditions improved the quality of the seed layer and retarded the speed of the hole size reduction. As a result, a metal seed layer with a via’s opening percentage of about 62% and a bottom seed layer thickness of 46.7 nm was fabricated by conventional sputtering using a tilting method. Using this seed layer, Cu was fully filled up in the vias after Cu electroplating in the condition of 7.5 mA/cm2 for 2 hours. Through Design of Experiments (DOE) the sputtering experiments for seed layers met the prerequisite of Cu filling electroplating. Furthermore the quality of seed layer was found to be improved. Therefore, the tilting sputtering method suggested in this experiment is suitable to an economical mass production method.