Realization of Balanced CMOS Device with Bulk Silicon Multiple-Gate MOSFET

Abstract

In these days, the demand for logic devices used for mobile devices gradually increases. Fabrication process scaling of these mobile logic devices is essential for their miniaturize and low-power consumption; however, conventional MOSFET devices now have faced serious scaling limit. Multiple-Gate MOSFET devices are recently researched for overcome these scaling limit. Since the gate electrode of Multiple-Gate MOSFETs possess maximized channel controllability, the devices can achieve improved sub-threshold characteristics. Therefore, the fabrication process of Multiple-Gate MOSFET devices can be scaled further. To maximize channel controllability, Multiple-Gate MOSFETs in previous research are fabricated on Silicon-On-Insulator wafer; however, these structures increases the product unit cost of the devices. In this thesis, Multiple-Gate MOSFET devices on bulk silicon wafer is researched. In various Multiple-Gate MOSFET structures, Dual-Gate FinFETs and Gate-All-Around MOSFETs are simulated. Simulated devices have HfO2 High-K dielectric material and Ti metal as the insulator and gate material of the devices. Simulation results show that the devices which have thin HfO2 insulator layer achieve better sub-threshold characteristics. Therefore, it can be considered that the insulator layer thickness should be thin within the limits that the insulator layer don’t cause gate leakage current. To utilize MOSFETs as the logic devices, both n-type and p-type MOSFET devices should be researched, and balanced CMOS device should be achieved. Since holes has lower mobility than electrons, p-type MOSFETs, however, have lower drain current than n-type MOSFETs. To achieve balanced CMOS, the drain current of p-type MOSFETs should be increased. In previous research, the method that the number of fin of p-type MOSFET is increased or that silicon orientation is modified for enhancement of hole mobility is used to compensate the lower drain current of p-type MOSFETs; however, the fin quantity method spends so many space of silicon wafer on fabricating device that the product unit cost of the device is increased. Moreover, the silicon orientation method is so complicated that the method cannot be applied to Multiple-Gate MOSFETs. In this thesis, as the Multiple-Gate MOSFETs have vertical-shaped channel, the method that the drain current is adjusted by modification of Multiple-Gate MOSFET is used to compensate the lower drain current of p-type MOSFETs. The balanced CMOS devices are achieved with the method in the device simulation. Multiple-Gate MOSFET devices can get the desired current amount by modification of the fin height.