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TSV 최소 배치에 기반한 3차원 집적회로의 전력 공급 네트워크 합성

Title
TSV 최소 배치에 기반한 3차원 집적회로의 전력 공급 네트워크 합성
Other Titles
Power Delivery Network Synthesis for Three-Dimensional Integrated Circuits based on Minimal Through-Silicon-Via Placement
Author
장철존
Alternative Author(s)
Jang, Cheoljon
Advisor(s)
정정화
Issue Date
2015-02
Publisher
한양대학교
Degree
Doctor
Abstract
In this dissertation, the methodologies are proposed to minimize the number of P/G TSVs and bumps while satisfying voltage (IR)-drop and electromigration (EM) constraints for three-dimensional power delivery network. Three-dimensional integrated circuits (3D ICs) with through-silicon-via (TSV) technology are emerging technology as a promising solution due to the shorter interconnects lengths, the smaller footprint area of the chip, the higher integration density, and more improved performance compared to 2D planar chip. However, several problems exist in the area of physical design for 3D ICs with TSV technology. Among them, power delivery network synthesis has been recognized as one of the most important issues in the industry. Power-ground (P/G) TSVs, which are used to supply and deliver power in 3D power delivery network, are limited in order to prevent severe placement and routing congestion of standard cell. P/G bumps are also limited due to the increased number of signal bumps. In this dissertation, 3D power delivery network synthesis methodologies are proposed as follows. First, incremental mesh structure selection technique is proposed to construct initial 3D power delivery network. This technique minimize the number of P/G TSVs and bumps while satisfying the IR-drop and EM constraints as increasing mesh pitch and mesh width from the minimum value determined by layout design rules for each die under the limited range of power routing resources. Second, circuit modeling and nodal analysis specialized for 3D power delivery network are presented to estimate the IR-drop of each node in 3D power delivery network. The degrees of IR-drop estimated are used for the parameters to place P/G TSVs and bumps. Through the nodal analysis, the IR-drop estimation can maintain the simplicity and scalability of circuit model for even large system. Finally, P/G TSV and bump co-placement algorithm is proposed to minimize the number of P/G TSVs and bumps while satisfying and minimizing the IR-drop and EM constraints. In this algorithm, the adjacent IR-drop violation nodes are identified using Delaunay triangulation, and the locations to place P/G TSVs and bumps are measured by considering the degrees of the IR-drop and the locations of the IR-drop violation nodes. P/G TSV and bump placement and the IR-drop re-estimation are repeated until the all of 3D power delivery network satisfy the IR-drop violation, and satisfy the IR-drop and EM constraints in all of power delivery network. The proposed methods have been implemented in C++/STL programming language. The various simulation results show that the proposed methods reduce the number of P/G TSVs and bumps by 10.1% and 52.9%, respectively, on average, while reducing the IR-drop and EM constraints by 3.2% and 24.9%, respectively, on average, compared to conventional methods.
URI
http://dcollection.hanyang.ac.kr/jsp/common/DcLoOrgPer.jsp?sItemId=000000082213http://repository.hanyang.ac.kr/handle/20.500.11754/129267
Appears in Collections:
GRADUATE SCHOOL[S](대학원) > NANOSCALE SEMICONDUCTOR ENGINEERING(나노반도체공학과) > Theses (Ph.D.)
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