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Operating mechanisms of multilevel memory devices with a floating gate consisting of nanocomposites

Title
Operating mechanisms of multilevel memory devices with a floating gate consisting of nanocomposites
Other Titles
나노복합체를 이용한 플로팅게이트를 가진 멀티레벨 메모리 소자의 동작 메커니즘에 관한 연구
Author
김유나
Alternative Author(s)
Kim, Yu Na
Advisor(s)
김태환
Issue Date
2016-02
Publisher
한양대학교
Degree
Master
Abstract
From the electronic technology and industry growth, memory devices are required to have high quality specification such as high intensity, flexibility, transparency and mass productivity. To demand these needs, study about Next-Generation Memory Devices are briskly ongoing from industry and academy both. In this thesis, 2 kinds of next-generation memory devices are being introduced, ReRAM and NFGM. These memories have strength at simple fabrication, mass productive, low power operation, potential to apply for flexibility. Nonvolatile memory devices based on a poly(4-vinylphenol) (PVP) layer containing Cu2ZnSnS4 (CZTS) nanoparticles were fabricated by using a simple spin-coating method. Capacitance-voltage (C-V) curves for Al/CZTS nanoparticles embedded in PVP layer/p-Si devices at 1 MHz showed a hysteresis with flat-band voltage (Vfb) shifts, which resulted from the existence of CZTS nanoparticle s acting as trap sites in the memory devices. The magnitudes of the Vfb corresponding to the memory windows shifts between 1.0 and 2.5 V, as determined from the C-V data at 1MHz, were dependent on the voltages applied to them memory device, indicative of multilevel characteristics for the memory effect. Nonvolatile organic memory devices were fabricated utilizing a graphene oxide (GO) layer embedded between two polystyrene (PS) layers. Capacitance-voltage (C-V) curves of the Al/PS/GO/PS/n-type Si devices clearly showed hysteresis behaviors with multilevel characteristics. The window margin of the nonvolatile memory devices increased from 1 to 7 V with increasing applied sweep voltages from 6 to 32 V. The cycling retention of the ON/OFF switching for the devices was measured by applying voltages between +15 and -15 V. While the capacitance of the memory devices at an ON state have retained as 230 pF up to 104cycles, that at an OFF state maintained as 16 pF during three times of repeated measurements. The measured retention characteristics will be retain up to 106cycles by extrapolation. The operating mechanisms of the nonvolatile organic memory devices were described by the C-V results and the energy band diagrams.
URI
http://dcollection.hanyang.ac.kr/jsp/common/DcLoOrgPer.jsp?sItemId=000000090574http://repository.hanyang.ac.kr/handle/20.500.11754/127068
Appears in Collections:
GRADUATE SCHOOL[S](대학원) > NANOSCALE SEMICONDUCTOR ENGINEERING(나노반도체공학과) > Theses (Master)
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