실험에 근거한 로우 해머링 고장 현상의 규명 및 분석

Abstract

DRAM is widely used for the memory storage since the simple cell structure, composed of a transistor and capacitor gives an advantage to facilitate the high capacity storage with low cost. However the DRAM cells should be periodically refreshed due to the leakage current in DRAM cells. The refresh operation recovers the leak charge in DRAM cells. Therefore DRAM cells should retain the stored value if they are refreshed within the cell retention time of 64 ms at minimum. However there was a case where the charge in a DRAM cell leaks faster, and the values of the stressed cells could not be retained with valid yet stressful hammered accesses to a row. This failure phenomenon is referred to as the row hammering failure which has become a serious problem. Commercial DDR3 SDRAM has been reported to suffer from the row hammering failure. Therefore it is important to prevent occurrence of the row hammering failure. In this thesis, the root cause of the row hammering failure is investigated by a SPICE simulation with the TCAD device model of a DRAM cell. The SPICE simulation shows that the stressful hammered accesses cause the charge in the victim cell to recombine with the electrons drifted from the channel of the aggressor access transistor. The electrons that drift toward the victim cell cause the threshold voltage of an access transistor to decrease. The threshold voltage reduction increases the sub-threshold leakage current in the victim cell, which accelerates the stored charge in a victim cell to be leaked. Experiments with commercial DDR3 discrete components from three major memory manufacturers were performed to confirm the validity of the SPICE simulation. The contributions of each in triggering and accelerating the failure mechanisms are investigated depending on the three test parameters—tRP, data pattern, and temperature— based on the experimental results. The failure probability was measured from the experiment with a total of 18 commercial DDR3 RDIMM modules of 2x nm process technology from three major memory manufacturers. Experimental result shows that the failure probability on cells and rows can be represented as the statistical model. First, the failure probability on cells is linearly proportional to the failure threshold by representing the failure probability distribution with the log-log plot. Therefore the model of failure probability on cells was proposed. Second, the failure probability distribution on rows of all modules follows the normal distribution. Therefore the failure probability of the modules from three different manufacturers was represented as the normal distribution function with the statistical parameters of mean and standard deviation. The statistical parameters of the modules from a manufacturer do not variate a lot. However the modules from the different manufacturer show a lot of difference in the failure probability. The failed cell distribution per row was investigated for three modules from three different manufacturers MA, MB and MC. In order to investigate the cell failure position, the number of failed cells is measured as the column address in a row and the components in the module. Based on the experimental result in the Chapter 6, the mitigation strategy is also discussed associated with the failed cell number in a row.