전력 소모 감소와 MTJ의 내구성 증가를 위한 STT-MRAM의 읽기 및 쓰기 통합회로

Abstract

STT-MRAM은 SRAM, DRAM 및 Flash Memory의 각각의 장점인 빠른 속도, 높은 집적도, 비휘발성과 적은 전력 소모라는 특징을 모두 가지고 있어 차세대 메모리로서 유망한 메모리이다. STT-MRAM의 셀을 구성하는 소자인 MTJ는 얇은 절연 막으로 분리된 두 개의 강자성층으로 구성되어있고, 두 개의 강자성층의 자화 방향에 따라 두 개의 안정한 상태를 가지고 있다. 두 개의 강자성층의 자화 방향이 평행하다면, 낮은 저항 값을 가지는 상태가 되며, 두 개의 강자성층의 자화 방향이 역 평행하다면, 높은 저항 값을 가지는 상태가 된다. MTJ의 상태전환시간은 매우 비대칭적이며 확률적인 상태전환을 가지고 있다. 따라서 일반적인 쓰기동작 방식에서는 MTJ의 상태전환이 완전히 이루어질 정도로 충분히 긴 시간동안 전류를 흘려주게 되고 이는 전력소모 및 MTJ의 내구성에대한 문제점을 야기한다.

본 논문에서는 MTJ의 확률적인 상태전환과 비대칭적인 상태전환시간으로부터 발생된 문제점들을 해결하기 위하여 제안되어 왔던 방식들을 설명하고, 기존의 제안된 방식들 보다 더 향상된 방식의 회로를 제안하고 설명한다. 제안하는 회로는 쓰기동작 시 MTJ의 상태를 감지하여 원하는 쓰기 값의 상태로의 상태전환이 발생하였을 때 쓰기동작을 종료한다. 따라서 MTJ의 확률적인 상태전환과 비대칭적인 상태전환시간에 대응할 수 있으며 불필요한 전력소모를 줄이고, MTJ의 내구성이 증가한다. 또한 본 논문에서 제안된 회로는 읽기 회로와 쓰기회로가 전류 드라이버에 의해 통합되어있으며, 읽기동작 및 쓰기동작 시 사용되는 기준 셀을 차동으로 구성하여 감지 마진을 증가시켰고, 쓰기동작에 사용되는 기준전압을 캐패시터에 저장하여 기준 셀의 신뢰성을 증가시키고 파워소모를 감소시켰다.

본 논문의 모든 디지털 로직 부품을 포함한 제안 된 회로는 CMOS 공정을 사용하여 설계하였고 SPICE-level 시뮬레이션을 사용하여 검증하였다.|STT-MRAM is a promising memory as the next generation memory because it has all of the advantages of SRAM, DRAM, and Flash Memory, such as high speed, high density, non-volatility, and low power consumption. To store information, STT-MRAMs use magneto-tunneling junctions (MTJs), which consist of two layers of ferromagnetic thin films separated by a thin insulating film. MTJs have two stable states, which are determined by the magnetization directions of the ferromagnetic layers. When the magnetization of the two layers are in parallel (P), it has low resistance (RL), and if the magnetizations are in anti-parallel (AP), it has high resistance (RH).

The switching of MTJ cells is highly asymmetric, in that the switching time from P-state to AP-state is significantly larger than that from AP-state to P-state even if the magnitude of the write current pulse is identical. Furthermore, the switching process of MTJs is highly stochastic, which means that the switching time of an MTJ has large spread even when the same cell is written repetitively with the current pulses of the same magnitude. When the switching time of MTJ cells have wide variations, a conservative write-circuit design would be to make the write current-pulse long enough so that a switching is guaranteed. However, this approach suffers from high energy consumption and subsequent degradation of MTJ cells from the repetitive use of excessively strong write pulses.

In this paper, I describe the conventional schemes that have been proposed to overcome stochastic behavior of MTJ switching and asymmetric switching time of MTJ. And then, I proposed a circuit for the read and write operations of STT-MRAM, which can reduce the energy consumption and improve the endurance of MTJs. In the proposed circuit, a single current driver is used for both read and write operations. The write operation uses a scheme in which the operation is terminated immediately after the state of the data cell switches to the desired state. To detect the state of the cell with minimum increase of power consumption, clocked comparators and differential compare circuits were employed. To increase the sense margin, a differential reference cell structure was used. The detailed digital logic part of the circuit has been fully designed. The proposed circuit has been implemented using a 0.13 μm CMOS technology, and SPICE-level simulations were performed to verify the successful operation of the circuit.; STT-MRAM is a promising memory as the next generation memory because it has all of the advantages of SRAM, DRAM, and Flash Memory, such as high speed, high density, non-volatility, and low power consumption. To store information, STT-MRAMs use magneto-tunneling junctions (MTJs), which consist of two layers of ferromagnetic thin films separated by a thin insulating film. MTJs have two stable states, which are determined by the magnetization directions of the ferromagnetic layers. When the magnetization of the two layers are in parallel (P), it has low resistance (RL), and if the magnetizations are in anti-parallel (AP), it has high resistance (RH).

The switching of MTJ cells is highly asymmetric, in that the switching time from P-state to AP-state is significantly larger than that from AP-state to P-state even if the magnitude of the write current pulse is identical. Furthermore, the switching process of MTJs is highly stochastic, which means that the switching time of an MTJ has large spread even when the same cell is written repetitively with the current pulses of the same magnitude. When the switching time of MTJ cells have wide variations, a conservative write-circuit design would be to make the write current-pulse long enough so that a switching is guaranteed. However, this approach suffers from high energy consumption and subsequent degradation of MTJ cells from the repetitive use of excessively strong write pulses.

In this paper, I describe the conventional schemes that have been proposed to overcome stochastic behavior of MTJ switching and asymmetric switching time of MTJ. And then, I proposed a circuit for the read and write operations of STT-MRAM, which can reduce the energy consumption and improve the endurance of MTJs. In the proposed circuit, a single current driver is used for both read and write operations. The write operation uses a scheme in which the operation is terminated immediately after the state of the data cell switches to the desired state. To detect the state of the cell with minimum increase of power consumption, clocked comparators and differential compare circuits were employed. To increase the sense margin, a differential reference cell structure was used. The detailed digital logic part of the circuit has been fully designed. The proposed circuit has been implemented using a 0.13 μm CMOS technology, and SPICE-level simulations were performed to verify the successful operation of the circuit.